參數(shù)資料
型號(hào)： BT458LPJ80
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁(yè)數(shù)： 17/60頁(yè)
文件大?。?/td> 647K
代理商： BT458LPJ80
Bt457/Bt458
1.0 Circuit Description
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1.3 MPU Interface
L45801 Rev. N
Conexant
1-9
Internal logic maintains an internal LOAD signal synchronous to CLOCK and
is guaranteed to follow the LD* signal by at least one, but not more than four,
clock cycles. This LOAD signal transfers the latched pixel and overlay data into a
second set of latches, which are then internally multiplexed at the pixel clock rate.
If 4:1 multiplexing is specified, only one rising edge of LD* should occur
every four clock cycles. If 5:1 multiplexing is specified, only one rising edge of
LD* should occur every five clock cycles. Otherwise, the internal LOAD
generation circuitry assumes it is not locked onto the LD* signal and
continuously attempts to resynchronize itself to LD*.
Color Selection
Each clock cycle, 8 bits of color information (P7:0) and 2 bits of overlay
information (OL1,0) for each pixel are processed by the read mask, blink mask,
and command registers. Through the control registers, individual bit planes can
be enabled or disabled for display, and/or blinked at one of four blink rates and
duty cycles.
To ensure blinking does not cause a color change to occur during the active
display time (i.e., in the middle of the screen), the Bt457/458 monitors the
BLANK* input to determine vertical retrace intervals. A vertical retrace interval
is recognized by determining that BLANK* has been a logical 0 for at least 256
LD* cycles.
The processed pixel data is then used to select which color palette entry or
overlay register is to provide color information. P[0] is the LSB when addressing
the color palette RAM.
Table 1-4
is the truth table used for color selection.
Video Generation
Every clock cycle, the selected color information, from the color palette RAMs or
overlay registers, is presented to the D/A converters.
The SYNC* and BLANK* inputs are pipelined to maintain synchronization
with the pixel data. They add appropriately weighted currents to the analog
outputs, producing the specific output levels required for video applications, as
described in
Figure 1-4
.
Varying output current from each D/A converter produces a corresponding
voltage level, used to drive the color CRT monitor. Only the green output (IOG)
on the Bt458 contains sync information.
Table 1-5
details how the SYNC* and
BLANK* inputs modify the output levels.
The D/A converters on the Bt457 and Bt458 use a segmented architecture in
which bit currents are routed to either the current output or GND by a
sophisticated decoding scheme. This architecture eliminates the need for
Table 1-4. Palette and Overlay Select Truth Table
CR[6]
OL[1]
OL[0]
P[7:0]
Addressed by Frame
1
0
0
$00
Color Palette Entry $00
1
0
0
$01
Color Palette Entry $01
:
:
:
:
:
1
0
0
$FF
Color Palette Entry $FF
0
0
0
$xx
Overlay Color 0
x
0
1
$xx
Overlay Color 1
x
1
0
$xx
Overlay Color 2
x
1
1
$xx
Overlay Color 3
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