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參數(shù)資料
| 型號： | BS208 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 小信號晶體管 |
| 英文描述： | P-channel enhancement mode vertical D-MOS transistor |
| 中文描述： | 200 mA, 200 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-92 |
| 封裝： | PLASTIC, SC-43, 3 PIN |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 64K |
| 代理商： | BS208 |
April 1995
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BS208
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified.
Notes
1.
2.
Measured at f = 1 MHz;
V
DS
= 25 V; V
GS
= 0.
V
GS
= 0 to 10 V;
I
D
= 250 mA;
V
DD
= 50 V.
SYMBOL
V
(BR)DSS
PARAMETER
CONDITIONS
V
GS
= 0
I
D
= 10
μ
A
V
DS
= 130 V
V
GS
= 0
V
DS
= 70 V
V
GS
= 0.2 V
V
GS
= 20 V
V
DS
= 0
V
GS
= V
DS
I
D
= 1 mA
V
GS
= 10 V
I
D
= 200 mA
V
DS
= 25 V
I
D
= 200 mA
note 1
note 1
note 1
note 2
note 2
MIN.
TYP.
MAX.
UNIT
drain-source breakdown
voltage
drain-source leakage current
200
-
V
I
DSS
1
μ
A
I
DSS
drain-source leakage current
25
μ
A
I
GSS
gate-source leakage current
100
nA
V
GS(th)
gate-source threshold
voltage
drain-source on-resistance
0.8
2.8
V
R
DS(on)
14
Y
fs
transfer admittance
100
200
mS
C
iss
C
oss
C
rss
t
on
t
off
input capacitances
output capacitance
feedback capacitance
turn-on time
turn-off time
55
20
90
30
15
10
30
pF
pF
pF
ns
ns
5
5
20
Fig.3 Switching times test circuit.
handbook, halfpage
MBB689
50
VDD =
50 V
ID
0 V
10 V
Fig.4 Input and output waveforms.
handbook, halfpage
MBB690
10 %
90 %
90 %
10 %
ton
toff
OUTPUT
INPUT
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