This activity unconditionally write-protects the external
SRAM as V
CC
falls below V
PFD
. If a memory access is in
progress to the external SRAM during power-fail detec-
tion, that memory cycle continues to completion before
the memory is write-protected. If the memory cycle is
not terminated within time t
WPT
, the chip enable output
is unconditionally driven high, write-protecting the con-
trolled SRAM.
As the supply continues to fall past V
PFD
, an internal
switching device forces V
OUT
to the external backup en-
ergy source.
CE
OUT
is held high by the V
OUT
energy
source.
During power-up, V
OUT
is switched back to the 5V sup-
ply as V
CC
rises above the backup cell input voltage
sourcing V
OUT
. CE
OUT
is held inactive for time t
CER
af-
ter the power supply has reached V
PFD
, independent of
theCE
IN
input, toallow for processor stabilization.
During power-valid operation, the CE
IN
input is passed
through to the CE
OUT
output with a propagation delay of
less than 12ns.
Figure 2 shows the hardware hookup for the external
RAM, battery, and crystal.
A
primary backup energy source input is provided on
the bq4845. The BC input accepts a 3V primary battery,
typically some type of lithium chemistry. Since the
bq4845 provides for reverse battery charging protection,
no diode or current limiting resistor is needed in series
with the cell. To prevent battery drain when there is no
valid data to retain, V
OUT
and CE
OUT
are internally iso-
lated from BC by the initial connection of a battery. Fol-
lowing the first application of V
CC
above V
PFD
, this iso-
lation is broken, and the backup cell provides power to
V
OUT
and CE
OUT
for theexternal SRAM.
The crystal should be located as close to X1 and X2 as
possible and meet the specifications in the Crystal
Specification Table. With the specified crystal, the
bq4845 RTC will be accurate to within one minute per
month at room temperature. In the absence of a crystal,
a 32.768 kHz waveform can be fed
grounded.
into X1 with X2
Power-On Reset
The bq4845 provides a power-on reset, which pulls the
RST pin low on power-down and remains low on power-
up for t
RST
after V
CC
passes V
PFD.
With valid battery
voltageon BC, RST remains valid for V
CC
= V
SS
.
6
Figure 2. bq4845 Application Circuit
Aug. 1995
bq4845/bq4845Y
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