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參數(shù)資料
| 型號(hào)： | BH16821ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State |
| 中文描述： | ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP2-56 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大小： | 80K |
| 代理商： | BH16821ADGG |
Philips Semiconductors
Product specification
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
1998 Feb 27
6
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±
0.5V
MIN
UNIT
MIN
TYP
MAX
MAX
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency
1
160
250
160
MHz
Propagation delay
nCP to nQx
1
1.3
1.1
2.4
2.0
3.3
2.6
1.3
1.1
3.7
3.0
ns
Output enable time
to High and Low level
3
4
1.4
1.2
2.5
2.3
3.3
3.0
1.4
1.2
4.1
3.7
ns
Output disable time
from High and Low level
3
4
1.6
1.3
3.2
2.3
4.1
3.1
1.6
1.3
4.8
3.3
ns
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
MIN
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±
0.5V
MIN
UNIT
TYP
MAX
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time, High or Low
nDx to nCP
2
1.8
1.8
1.2
–0.9
1.8
1.8
ns
Hold time, High or Low
nDx to nCP
2
1.0
1.0
0.8
–1.0
1.0
1.0
ns
nCP pulse width
High or Low
1
2.5
2.5
0.8
1.0
2.5
2.5
ns
AC WAVEFORMS
V
M
SH00005
nCP
nQx
V
M
t
w
(H)
t
PH
L
V
M
t
PLH
1/f
MAX
V
M
V
M
t
w
(L)
0V
V
OH
V
OL
3.0V or V
CC
whichever
is less
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock frequency
t
h
(H)
t
s
(H)
CP
SH00006
V
M
V
M
V
M
V
M
V
M
V
M
t
h
(L)
t
s
(L)
nDx
0V
3.0V or V
CC
whichever
is less
0V
3.0V or V
CC
whichever
is less
Waveform 2. Data Setup and Hold Times
V
Y
V
M
V
M
V
M
nQx
t
PZH
t
PHZ
SH00007
nOE
0V
V
OH
0V
3.0V or V
CC
whichever
is less
Waveform 3. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
X
V
OL
V
M
V
M
V
M
nQx
t
PZL
t
PLZ
SH00008
nOE
0V
0V
3.0V or V
CC
3.0V or V
CC
whichever
is less
Waveform 4. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BH16821ADL | 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State |
| BH16823ADGG | 18-bit bus interface D-type flip-flop with reset and enable 3-State |
| BH16823ADL | 18-bit bus interface D-type flip-flop with reset and enable 3-State |
| BH16825ADGG | 18-bit buffer/line driver; non-inverting 3-State |
| BH16825ADL | 18-bit buffer/line driver; non-inverting 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BH16821ADL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State |
| BH16823ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit bus interface D-type flip-flop with reset and enable 3-State |
| BH16823ADL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit bus interface D-type flip-flop with reset and enable 3-State |
| BH16825ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit buffer/line driver; non-inverting 3-State |
| BH16825ADL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit buffer/line driver; non-inverting 3-State |
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