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參數(shù)資料
| 型號(hào)： | BH16260DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | 12-bit to 24-bit multiplexed D-type latches 3-State |
| 中文描述： | ABT SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP2-56 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | BH16260DGG |
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1998 Feb 10
8
AC WAVEFORMS
V
M
= 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
t
w
V
M
V
M
3V
0V
INPUT
SA00437
Figure 1. Pulse duration
V
M
V
M
3V
0V
INPUT
t
PLH
V
M
V
M
V
OH
V
OL
t
PHL
V
OH
V
OL
V
M
V
M
t
PHL
t
PLH
OUTPUT
OUTPUT
SA00438
All input pulses are supplied by generators having the following
characteristics: PRR
≤
10MHz, Z
O
= 50
, t
r
≤
2.5ns, t
f
≤
2.5ns.
Figure 2. Propagation delay times;
inverting and non-inverting outputs
V
M
V
M
3V
0V
DATA INPUT
0V
3V
TIMING INPUT
V
M
t
su
t
h
SA00439
Figure 3. Setup and hold times
V
M
V
M
3V
0V
OUTPUT
CONTROL
t
PZL
V
M
V
OL
+ 0.3V
3.5V
V
OL
t
PLZ
V
OH
≈
0V
V
OH
– 0.3V
t
PZH
t
PHZ
OUTPUT
WAVEFORM 1
S1 AT 7V
V
M
OUTPUT
WAVEFORM 2
S1 AT OPEN
SA00440
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
C
= 50pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
500
500
FROM OUTPUT UNDER TEST
S1
7V
OPEN
GND
Load Circuit for Outputs
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
7V
Open
SA00441
Figure 5. Test load circuit
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