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參數(shù)資料
| 型號： | BH16260DGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 12-bit to 24-bit multiplexed D-type latches 3-State |
| 中文描述： | ABT SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP2-56 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 79K |
| 代理商： | BH16260DGG |
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
1998 Feb 10
6
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= –40
°
C
°
C
Min
UNIT
Min
Typ
Max
Max
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
–0.8
–1.2
–1.2
V
2.5
2.9
2.5
V
V
OH
High-level output voltage
3.0
3.4
3.0
V
2.0
2.4
2.0
V
V
OL
Low-level output voltage
0.42
0.55
0.55
V
I
Input leakage current
V
CC
= 5.5V; V
I
= V
CC
or GND
Control
pins
Data pins
±
0.01
±
1
±
1
μ
A
I
V
CC
= 5.5V; V
I
= V
CC
or GND
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.0V; V
O
= 0.5V;
V
I
CC
; V
OE
= V
CC
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
Outputs enabled, one input at 3.4V, other
inputs at V
CC
or GND; V
CC
= 5.5V
±
3
±
5
μ
A
A or B
ports
75
75
I
HOLD
Bus Hold current
–75
±
500
–75
±
500
μ
A
I
OFF
Power-off leakage current
±
5.0
±
100
±
100
μ
A
I
PU
/I
PD
Power-up/down 3-State
output current
±
60
±
200
±
200
μ
A
I
OZH
I
OZL
I
CEX
I
O
3-State output High current
1.0
10
10
μ
A
μ
A
μ
A
mA
3-State output Low current
–1.0
–10
–10
Output high leakage current
Output current
1
50
50
–50
–100
–225
–50
–225
0.2
1.5
1.5
I
CC
Quiescent supply current
8
19
19
mA
0.1
1.0
1.0
I
CC
Additional supply current per
input pin
2
0.1
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state.
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