參數(shù)資料
型號(hào)： BCM5802
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144
封裝： 28 X 28 MM, QFP-144
文件頁(yè)數(shù)： 10/41頁(yè)
文件大?。?/td> 571K
代理商： BCM5802
18
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The output buffer in each IOC has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces board-level noise and adds a nominal timing delay to the
output buffer delay (tOD) parameter. The fast slew rate should be used for
speed-critical outputs in systems that are adequately protected against
noise. Designers can specify the slew rate on a pin-by-pin basis during
design entry or assign a default slew rate to all pins on a global basis. The
slew rate control affects both rising and falling edges of the output signals.
Output
Conguration
The MAX 9000 device architecture supports the MultiVolt I/O interface
feature, which allows MAX 9000 devices to interface with systems of
differing supply voltages. The 5.0-V devices in all packages can be set for
3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply. With
a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore
compatible with 3.3-V and 5.0-V inputs.
Table 6. Peripheral Bus Sources
Peripheral Control
Signal
Source
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
OE0/ENA0
Row C
Row E
Row F
Row G
OE1/ENA1
Row B
Row E
Row F
OE2/ENA2
Row A
Row E
OE3/ENA3
Row B
OE4/ENA4
Row A
OE5
Row D
OE6
Row C
OE7/CLR1
Row B/GOE
CLR0/ENA5
Row A/GCLR
CLK0
GCLK1
CLK1
GCLK2
CLK2
Row D
CLK3
Row C
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