參數(shù)資料
型號(hào)： B900M24FXX16I
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 80 MHz, OTHER DSP, PQCC44
文件頁(yè)數(shù)： 13/100頁(yè)
文件大?。?/td> 1547K
代理商： B900M24FXX16I
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
1
Features ............................................................................................................................................................. 1
2
Description ......................................................................................................................................................... 1
3
Pin Information ................................................................................................................................................... 8
4
Hardware Architecture ..................................................................................................................................... 15
4.1 B900 Architectural Overview .................................................................................................................... 15
4.1.1
DSP1600 Core ................................................................................................................................ 18
4.1.2
Dual-Port RAM (DPRAM) ................................................................................................................ 18
4.1.3
Read-Only Memory (ROM) .............................................................................................................. 18
4.1.4
Timers .............................................................................................................................................. 18
4.1.5
Watchdog Timer .............................................................................................................................. 18
4.1.6
Input/Output Ports (IOP) .................................................................................................................. 18
4.1.7
JTAG ............................................................................................................................................... 18
4.1.8
Synchronous Serial Interface Units (SSI) ........................................................................................ 19
4.1.9
Clock Generation ............................................................................................................................. 19
4.1.10 Dual-Channel Serial I/O Port (SIO) ................................................................................................. 19
4.1.11 Bit Manipulation Unit (BMU) ............................................................................................................ 19
4.2 DSP1600 Core Architectural Overview .................................................................................................... 20
4.2.1
System Cache and Control Section (SYS) ...................................................................................... 22
4.2.2
Data Arithmetic Unit (DAU) .............................................................................................................. 22
4.2.3
Y Space Address Arithmetic Unit (YAAU) ....................................................................................... 22
4.2.4
X Space Address Arithmetic Unit (XAAU) ....................................................................................... 22
4.3 Interrupts, Trap, and Low-Power Standby Mode ...................................................................................... 22
4.3.1
Interruptibility ................................................................................................................................... 23
4.3.2
Vectored Interrupts .......................................................................................................................... 23
4.3.3
External Interrupt Pin (INTB) ........................................................................................................... 23
4.3.4
Clearing Interrupts ........................................................................................................................... 24
4.3.5
Power-Saving Modes ...................................................................................................................... 24
4.4 Memory Maps and Wait-States ................................................................................................................ 24
4.4.1
Instruction/Coefficient Memory Map Selection ................................................................................ 24
4.4.2
Data Memory Map Selection ........................................................................................................... 25
4.5 Clock Generation ...................................................................................................................................... 26
4.5.1
Functional Overview ........................................................................................................................ 26
4.5.2
Core Clock Switching ...................................................................................................................... 28
4.6 Synchronous Serial Interface (SSI) .......................................................................................................... 29
4.6.1
SSI Operation .................................................................................................................................. 30
4.7 I/O Ports (IOP) .......................................................................................................................................... 31
4.7.1
IOP Operation.................................................................................................................................. 31
4.7.2
IOPA Interrupt Circuitry .................................................................................................................... 31
4.7.3
Pin Multiplexing Control .................................................................................................................. 32
4.8 Timers ....................................................................................................................................................... 33
4.9 Watchdog Timer ....................................................................................................................................... 33
4.10 Dual-Channel Serial I/O Port (SIO) for B900 .......................................................................................... 34
4.10.1 B900 SIO Architecture..................................................................................................................... 35
4.10.2 B900 SIO Operation ........................................................................................................................ 36
4.10.3 B900 SIO Programming Examples .................................................................................................. 37
4.11 Bit Manipulation Unit (BMU) .................................................................................................................... 38
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