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參數(shù)資料
| 型號： | AX88790L |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| 中文描述： | 一個10/100Base 3合1的PCMCIA快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 8/60頁 |
| 文件大?。?/td> | 633K |
| 代理商： | AX88790L |
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ASIX ELECTRONICS CORPORATION
8
AX88790 L 3-in-1 PCMCIA Fast Ethernet Controller
2.2 EEPROM Signals Group
SIGNAL
TYPE
EECS
O
EECK
O/PD
EEDI
O
EEDO
I/PU
PIN NO.
51
50
49
48
DESCRIPTION
EEPROM Chip Select: EEPROM chip select signal.
EEPROM Clock: Signal connected to EEPROM clock pin.
EEPROM Data In: Signal connected to EEPROM data input pin.
EEPROM Data Out: Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL
TYPE
RXD[3:0]
CRS
I/PD
PIN NO.
98 – 95
DESCRIPTION
I/PU
Receive Data: RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense: Asynchronous signal CRS is asserted by the PHY when
either transmit or receive medium is non-idle.
Receive Data Valid: RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
No Support Receive Error: RX_ER is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
99
Receive Clock: RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV, RXD[3:0] and
RX_ER signals from the PHY to the MII port.
101
Collision: this signal is driven by PHY when collision is detected.
108
Transmit Enable: TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
112 – 109 Transmit Data: TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
107
Transmit Clock: TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
67
Station Management Data Clock: The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
66
Station Management Data Input / Output: Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII specification.
100
RX_DV
I/PD
102
RX_ER
(Omit)
RX_CLK
I/PU
COL
TX_EN
I/PD
O
TXD[3:0]
O
TX_CLK
I/PU
MDC
O/PU
MDIO
I/O/PU
Tab - 3 MII interface signals group
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