參數(shù)資料
型號： AX88790L
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller
中文描述： 一個10/100Base 3合1的PCMCIA快速以太網(wǎng)控制器
文件頁數(shù)： 17/60頁
文件大小： 633K
代理商： AX88790L
ASIX ELECTRONICS CORPORATION
17
AX88790 L 3-in-1 PCMCIA Fast Ethernet Controller
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
FIELD
7:3
2
R/W/C
-
R/W
DESCRIPTION
Reserved
PPwrDwn : PHY power down setting
While this bit set to 1, AX88790 will force embedded PHY into power down mode. As for
PPWDN is active high or active low. Please refer section 2.9 Power on configuration setup
signal cross-reference table.
Note: The master control of Power Down mode is place on Bit 0 of CFL. If user want to
enable power down mode, must set the relative bit of EEPROM that map to bit 0 of CFL
register to logic 1. When this bit is set to 1, the LAN will go into power down mode. At
power down mode AX88790 will disable MAC transmitting and receiving operation. But
the host interface will not be affected.
Intr: Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
IntrAck: Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
1
R
0
R
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to access the
LAN specific registers (MAC Core Registers).
I/O Base Register 0
FIELD
7:0
I/O Base Register 1
FIELD
7:0
R/W/C
R/W
DESCRIPTION
Base I/O address bit 7 – 0.
R/W/C
R/W
DESCRIPTION
Base I/O address bit 15 – 8.
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