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參數(shù)資料
| 型號： | AX88790L |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| 中文描述： | 一個(gè)10/100Base 3合1的PCMCIA快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大小： | 633K |
| 代理商： | AX88790L |
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ASIX ELECTRONICS CORPORATION
36
AX88790 L 3-in-1 PCMCIA Fast Ethernet Controller
4.4.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions
FIELD
TYPE
30.15 (Test10TX)
R/W
When high and 10Base-T is powered up, a continuous 10 MHz signal
(1111) will be transmitted. This is only meant for testing. Default 0.
30.14 (RxPLLEn)
R/W
When high, all 10Base-T logic will be powered up when the link is up.
Otherwise, portions of the logic will be powered down when no data is being
received to conserve power. Default is 0.
30.13 (JAB_DIS)
R/W
Jabber Disable.
When this bit is 1, disables the jabber function of the
10Base-T receive. Default is 0.
30.12:7 (UNUSED)
R/W
Unused.
Read as 0.
30.6 (LITF_ENH)
R/W
Enhanced Link Integrity Test Function.
When high, function is enabled.
This is ORed with the LITF_ENH input. Default is 0.
30.5 (HBT_EN)
R/W
Heartbeat Enable.
When this bit is a 1, the heartbeat function will be
enabled. Valid in 10Mbits/s mode only.
30.4 (ELL_EN)
R/W
Extended Line Length Enable.
When this bit is a 1, the receive squelch
levels are reduced from a nominal 435 mV to 350 mV, allowing reception of
signals with a lower amplitude. Valid in 10Mbits/s mode only.
30.3 (APF_EN)
R/W
Autopolarity Function Disable.
When this bit is a 0 and the PHY is in
10Mbits/s mode, the autopolarity function will determine if the TP link is
wired with a polarity reversal.
If there is a polarity reversal, the PHY will assert the APS bit (register 28, bit
6) and correct the polarity reversal. If this bit is a 1 and the device is in
10Mbits/s mode, the reversal will not be corrected.
30.2 (RESERVED)
R/W
Reserved
.
30.1 (SERIAL _SEL)
R/W
Serial Select.
When this bit is set to a 1, 10Mbits/s serial mode will be
Selected. When the PHY is in 100Mbits/s mode, this bit will be ignored.
30.0 (ENA_NO_LP)
R/W
No Link Pulse Mode.
Setting this bit to a 1 will allow 10Mbits/s operation
with link pulses disabled. If the PHY is configured for 100Mbits/s operation,
setting this bit will not affect operation.
DESCRIPTION
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