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參數(shù)資料
| 型號： | AX88772 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB to 10/100 Fast Ethernet/HomePNA Controller |
| 中文描述： | USB至10/100快速以太網(wǎng)/電話線網(wǎng)絡控制器 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 393K |
| 代理商： | AX88772 |
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
Input, 2.5V with 3.3V tolerant
I3
Input, 3.3V
I5
Input, 3.3V with 5V tolerant
O2
Output, 2.5V with 3.3V tolerant
O3
Output, 3.3V
O5
Output, 3.3V with 5V tolerant
B
Bi-directional I/O
B2
B5
PU
PD
P
S
Bi-directional I/O, 2.5V with 3.3V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
Internal Pull Up (75K)
Internal Pull Down (75K)
Power Pin
Schmitt Trigger
Table 1: Pinout Description
Pin Name
Type
Pin No
Pin Description
USB Interface
USB 2.0 data positive pin.
USB 2.0 data negative pin.
USB 1.1 data positive pin. Please connect to DP through a 39ohm
(+/-1%) serial resistor.
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
VBUS pin input. Please connect to USB bus power.
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate.
12Mhz crystal or oscillator clock output.
For USB PHY’s internal biasing. Please connect to AGND through a
12.1Kohm (+/-1%) resistor.
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Interface
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
Station Management Interrupt input.
MII Interface
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII interface.
110, 109,
108, 107
RX_CLK by PHY.
105
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [3:0].
106
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
116
Collision Detected. COL is driven high by PHY when the collision is
detected.
DP
DM
DPRS
B
B
B
32
31
36
DMRS
B
35
VBUS
XIN12M
I5/PD/S
I3
10
26
XOUT12M
RREF
O3
I
27
30
RPU
I
34
MDC
O2
121
MDIO
B2/PU
120
MDINT
I2/PU
117
RX_CLK
I2
104
RXD [3:0]
RX_DV
I2
Receive Data. RXD [3:0] is driven synchronously with respect to
I2
RX_ER
I2
COL
I2
ASIX ELECTRONICS CORPORATION
6
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