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參數(shù)資料
| 型號： | AX88772 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB to 10/100 Fast Ethernet/HomePNA Controller |
| 中文描述： | USB至10/100快速以太網(wǎng)/電話線網(wǎng)絡控制器 |
| 文件頁數(shù)： | 14/42頁 |
| 文件大?。?/td> | 393K |
| 代理商： | AX88772 |
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
4.1.4 Phy Register Offset for Interrupt Endpoint (0Fh)
Bit 14
Bit 13
Reserved
Bit 7
Bit 6
Bit 5
Reserved
Phy Register Offset 1: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 5 and 6 of Interrupt Endpoint packet.
Phy Register Offset 2: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 7 and 8 of Interrupt Endpoint packet.
4.1.5 Max Packet Size High/Low Byte (10h)
Fill in this field the maximum RX/TX MAC frame size supported by this ASIC. The number must be even number in
terms of byte and should be less than or equal to 2500 bytes.
4.1.6 Primary/Secondary Phy_Type and Phy_ID (11h)
The 3 bits Phy_Type field for both Primary and Secondary Phy is defined as follows,
3’b000: 10/100 Ethernet Phy or 1M HOME Phy.
3’b111: non-supported Phy. For example, the High Byte value of “E0h” means that secondary Phy is not supported.
Note that the Phy_ID of the embedded 10/100 Ethernet PHY is being assigned to 5’b1_0000.
4.1.7 Pause Frame High Water and Low Water Mark (12H)
When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet
receive throughput performance in a great deal. The High Water Mark is the threshold to trigger sending of Pause frame
and the Low Water Mark is the threshold to stop sending of Pause frame. Note that each free buffer count here represents
256 bytes of packet storage space in SRAM.
Total free buffer count = 80
Stop sending Pause frame when free buffer > Low Water Mark
Start sending Pause frame when free buffer < High Water Mark
0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Phy Register Offset 1
Bit 3
Bit 2
Phy Register Offset 2
Bit 4
Bit 1
Bit 0
ASIX ELECTRONICS CORPORATION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88772_07 | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100 Fast Ethernet/HomePNA Controller |
| AX88772A | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88772ALF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88772B | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88796C -- 低功耗 SPI或Non-PCI以太網(wǎng)控制器與方案 |
| AX88772BLF | 制造商:ASIX Electronics Corporation 功能描述: |
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