
AX88141 PRELIMINARY
ASIX ELECTRONICS CORPORATION
24
CONFIDENTIAL
4.2.10 Interrupt Enable Register (REG7)
1.
2.
The interrupt enable register (REG7) enables the interrupts reported by REG5.
Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Field
31:17
16
R/W/C
-
R/W
Description
Reserved
NI - Normal Interrupt Summary Enable
When set, normal interrupt is enabled.
When reset, no normal interrupt is enabled. This bit (REG7<16>) enables the following bits :
CSR5<0>
CSR5<2>
CSR5<6>
CSR5<10>
CSR5<11>
AI - Abnormal Interrupt Summary Enable
When set, abnormal interrupt is enabled.
When reset, no abnormal interrupt is enabled. This bit (REG7<15>) enables the following bits :
CSR5<1>
CSR5<3>
CSR5<5>
CSR5<7>
CSR5<8>
CSR5<9>
CSR5<11>
FBE - Fatal Bus Error interrupt enable. Active high.
GPT - General purpose Timer interrupt Enable. Active high.
ETE - Early Transmit Interrupt Enable. Active high.
RW - Receive Watchdog Time out interrupt Enable. Active high
RS - Receive Stopped interrupt Enable. Active high.
RU - Receive Buffer Unavailable interrupt Enable. Active high.
RI - Receive Interrupt Enable. Active high.
UN - under-flow interrupt Enable. Active high.
Reserved.--Written as “0” for future compatibility concern.
TJ - Transmit Jabber Time out interrupt Enable. Active high.
TU - Transmit Buffer Unavailable interrupt Enable. Active high.
TS - Transmission Stopped interrupt Enable. Active high.
TI - Transmit Interrupt Enable. Active high.
Transmit interrupt
Transmit buffer unavailable
Receive interrupt
Early transmit interrupt
General-purpose timer expired
transmit process stopped
transmit jabber time-out
transmit under-flow
receive buffer unavailable
receive process stopped
receive watchdog time-out
fatal bus error
15
R/W
13
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Tab - 29 REG7 Interrupt Enable Register Description
4.2.11 Missed Frame and Overflow Flag (REG8)
Field
R/W
Description
31: 18
-
Reserved
17
R/C
Overflow Flag
Indicates the frames discarded because of overflow. The flag clears when read.
16 : 1
-
Reserved
0
R/C
Missed Frame Flag
Indicates the frames discarded because no host receive descriptors were available. The flag clears when read.
Tab - 30 REG8 Missed Frame and Overflow Counter Description