參數(shù)資料
型號(hào): AX88141
廠商: ASIX Electronics Corporation
英文描述: 100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT
中文描述: 100BASE-TX/FX PCI總線的快速以太網(wǎng)MAC控制器電源管理
文件頁(yè)數(shù): 20/43頁(yè)
文件大小: 308K
代理商: AX88141
AX88141 PRELIMINARY
ASIX ELECTRONICS CORPORATION
20
CONFIDENTIAL
4.2.5 Receive Poll Demand (REG2)
FIELD
R/W/C
31:0
W
RPD - Receive Poll Demand
When written with any value, the AX88141 checks for receive descriptors to be required. If no descriptor is available,
the receive process returns to the suspended states and REG5<7> is not asserted. If the descriptor is available the receive
process resumes.
DESCRIPTION
Tab - 23 REG2 Receive Poll Demand Register Description
4.2.6 Receive List Base Address (REG3)
1.
The register is used to point the AX88141 to the start of receive descriptors list.
2.
The descriptor list resides in physical memory space and must be longword aligned. The
AX88141 behaves UNPREDICTABLY when the list are not longword aligned.
3.
Writing to REG3 is permitted only when receive process is in the stopped state. That is, the
REG3 must be written before the receive START command is given .
REG3 Receive List Base Address Register Description
FIELD
R/W/C
31:2
R/W
Start of receive list
1:0
R/W
Must be 00 for longword alignment
DESCRIPTION
Tab - 24 REG3 Receive List Base Address Register Description
4.2.7 Transmit List Base Address (REG4)
1.
The register is used to point the AX88141 to the start of transmit descriptors list.
2.
The descriptor list resides in physical memory space and must be long-word aligned. The
AX88141 behaves UNPREDICTABLY when the list are not long-word aligned.
3.
Writing to REG4 is permitted only when transmit process is in the stopped state. That is, the
REG4 must be written before the transmit START command is given .
FIELD
31:2
1:0
R/W/C
R/W
R/W
DESCRIPTION
Start of transmit list
Must be 00 for long-word alignment
Tab - 25 REG4 Transmit List Base Address Register Description
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