- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3804 > ATTINY84A-CCU (Atmel)IC MCU 8BIT 8K FLASH 15UFBGA PDF資料下載
參數(shù)資料
| 型號： | ATTINY84A-CCU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 40/135頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 8K FLASH 15UFBGA |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | AVR® ATtiny |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | USI |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 15-UFBGA |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁
134
32015G–AVR32–09/09
AT32AP7001
15.4.2
Power Management
Edge triggered interrupts are available in all sleep modes except Deepdown. Level triggered
interrupts and the NMI interrupt are available in all sleep modes.
15.4.3
Interrupt
The EIC interrupt lines are connected to internal sources of the interrupt controller. Using the
External Interrutps requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
15.5
Functional Description
15.5.1
External Interrupts
Each external interrupt pin EXTINTn can be configured to produce an interrupt on rising or fall-
ing edge, or high or low level. External interrupts are configured by the MODE, EDGE, and
LEVEL registers. Each interrupt n has a bit INTn in each of these registers.
Similarly, each interrupt has a corresponding bit in each of the interrupt control and status regis-
ters. Writing 1 to the INTn strobe in IER enables the external interrupt on pin EXTINTn, while
writing 1 to INTn in IDR disables the external interrupt. IMR can be read to check which inter-
rupts are enabled. When the interrupt triggers, the corresponding bit in ISR will be set. For edge
triggered interrupts, the flag remains set until the corresponding strobe bit in ICR is written to 1.
For level triggered interrupts, the flag remains set for as long as the interrupt condition is present
on the pin.
Writing INTn in MODE to 0 enables edge triggered interrupts, while writing the bit to 1 enables
level triggered interrupts.
If EXTINTn is configured as an edge triggered interrupt, writing INTn in EDGE to 0 will trigger the
interrupt on falling edge, while writing the bit to 1 will trigger the interrupt on rising edge.
If EXTINTn is configured as a level triggered interrupt, writing INTn in LEVEL to 0 will trigger the
interrupt on low level, while writing the bit to 1 will trigger the interrupt on high level.
15.5.1.1
Synchronization of external interrupts
The pin value of the EXTINTn pins is normally synchronized to the CPU clock, so spikes shorter
than a CPU clock cycle are not guaranteed to produce an interrupt. In Stop mode, spikes shorter
than a 32KHz clock cycle are not guaranteed to produce an interrupt. In Deepdown mode, only
unsynchronized level interrupts remain active, and any short spike on this interrupt will wake up
the device.
15.5.2
NMI Control
The Non-Maskable Interrupt of the CPU is connected to the NMI_N pin through masking logic in
the External Interrupt Controller. This masking ensures that the NMI will not trigger before the
CPU has been set up to handle interrupts. Writing the EN bit in the NMIC register enables the
NMI interrupt, while writing EN to 0 disables the NMI interrupt. When enabled, the interrupt trig-
gers whenever the NMI_N pin is negated.
The NMI_N pin is synchronized the same way as external level interrupts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 008016038217751V | CABLE CLAMP W/STRAIN RELIEF #38 |
| 308237981000100 | COVER ASSMBLY FOR DIN CONN |
| 308237951000100 | COVER ASSMBLY FOR DIN CONN |
| 308237981000300 | COVER ASSMBLY FOR DIN CONN |
| 308237951001100 | COVER ASSMBLY FOR DIN CONN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATTINY84A-CCUR | 功能描述:8位微控制器 -MCU 20MHz Ind. Grade RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY84A-MF | 制造商:Atmel Corporation 功能描述:IC MCU 8BIT 8KB FLASH 20QFN 制造商:Atmel Corporation 功能描述:AVR, 8K FLASH 2K SRAM, 1KB EEPROM - 16MHz, 4x4 WQFN, High Grade +125C, Green |
| ATTINY84A-MFR | 制造商:Atmel Corporation 功能描述:16MHZ,4X4WQFN,HIGH GRADE +125C,GREEN,T&R - Tape and Reel 制造商:Atmel Corporation 功能描述:IC MCU 8BIT 8KB FLASH 20QFN 制造商:Atmel Corporation 功能描述:AVR, 8K FLASH 2K SRAM, 1KB EEPROM - 16MHz,4x4WQFN,High Grade +125C,Green,T&R |
| ATTINY84A-MMH | 功能描述:8位微控制器 -MCU 20MHz Ind. Grade RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ATTINY84A-MMHR | 功能描述:8位微控制器 -MCU 20MHz Ind Grade RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。