參數(shù)資料
型號: ATTINY84A-CCU
廠商: Atmel
文件頁數(shù): 4/135頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 8K FLASH 15UFBGA
標(biāo)準(zhǔn)包裝: 490
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 15-UFBGA
包裝: 托盤
101
32015G–AVR32–09/09
AT32AP7001
NEXUS_ACCESS or a MEMORY_ACCESS JTAG command is loaded into the instruction regis-
ter before entering sleep mode some clocks are left running to enable debugging of the system.
This will increase the power consumption of the device. If the part entered static mode without a
NEXUS_ACCESS ot MEMORY_ACCESS instruction loaded into the JTAG instruction register
an external reset is the only way for the debugger to get the part out of the sleep mode.
When not debugging a program and using sleep modes the JTAG should always have the
IDCODE instruction loaded into the JTAG instruction register and the OCD system should be
disabled. Otherwise some clocks may be left running, increasing the power consumption.
11.5.7
Generic clocks
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined number of generic clocks, that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.
Figure 11-4. Generic clock generation
11.5.7.1
Enabling a generic clock
A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
resulting in the output frequency:
f
GCLK = fSRC / (2*(DIV+1))
Divider
0
1
Osc0 clock
PLL0 clock
PLLSEL
OSCSEL
Osc1 clock
PLL1 clock
Generic Clock
DIV
0
1
DIVEN
Mask
CEN
Sleep
Controller
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