參數(shù)資料
型號(hào)： ATSAM3SD8CA-CU
廠商： Atmel
文件頁數(shù)： 41/57頁
文件大?。?/td> 0K
描述： IC MCU 2X256KB CORTEX-M3 100-QFN
標(biāo)準(zhǔn)包裝： 260
系列： SAM3S
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 64MHz
連通性： EBI/EMI，I²C，IrDA，MMC，SPI，SSC，UART/USART，USB
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 79
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： *
包裝： *
46
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Quadrature decoder
– Advanced line filtering
– Position / revolution / speed
2-bit Gray Up/Down Counter for Stepper Motor
11.7
Pulse Width Modulation Controller (PWM)
One Four-channel 16-bit PWM Controller, 16-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
channel
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
Synchronous Channel mode
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
of periods
Connection to one PDC channel
– Provides Buffer transfer without processor intervention, to update duty cycle of
synchronous channels
Two independent event lines which can send up to 4 triggers on ADC within a period
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