1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATMEGA8HVA-4CKU
寤犲晢锛� Atmel
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鏂囦欢澶�?銆�?/td> 0K
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鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 MCU Product Line Introduction
megaAVR Introduction
妯欐簴鍖呰锛� 364
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
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RAM 瀹归噺锛� 512 x 8
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鍖呰锛� 鎵樼洡
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ATSTK500-ND - PROGRAMMER AVR STARTER KIT
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69
8024A鈥揂VR鈥�04/08
ATmega8HVA/16HVA
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 15-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-
ure 15-5 on page 68 are not shown in the succeeding tables. The overriding signals are
generated internally in the modules having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 15-2.
Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
PVOE
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
PVOV
Port Value
Override Value
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
PTOE
Port Toggle
Override Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
DIEOV
Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the schmitt trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
AIO
Analog
Input/Output
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ATSAM3N4AA-AU MCU FLASH 48-QFP
ATSAM3SD8CA-CU IC MCU 2X256KB CORTEX-M3 100-QFN
ATSAM3U1EB-CU IC MCU 64KB CORTEX-M3 144-TFBGA
ATSAM3X8EA-CU IC MCU 2X256KB CORTEX-M3 144-BGA
ATTINY12V-1SUR IC AVR MCU 1K FLASH 4MHZ 8-SOIC
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