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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATMEGA649V-8MI |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 103/146闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC AVR MCU FLASH 64K 1.8V 64QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | megaAVR Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 260 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 閫ｉ€氭€э細 | SPI锛孶ART/USART锛孶SI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 53 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 64KB锛�32K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 2K x 8 |
| RAM 瀹归噺锛� | 4K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 64-VFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 鎵樼洡 |
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2010-2012 Microchip Technology Inc.
DS41440C-page 343
PIC16(L)F1825/1829
MOVWI
Move W to INDFn
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
n
[0,1]
mm
[00,01, 10, 11]
-32
k 31
Operation:
W
INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
None
Mode
Syntax
mm
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
NOP
No Operation
Syntax:
[ label ]
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
Words:
1
Cycles:
1
Example:
NOP
OPTION
Load OPTION_REG Register
with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)
OPTION_REG
Status Affected:
None
Description:
Move data from W register to
OPTION_REG register.
Words:
1
Cycles:
1
Example:
OPTION
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to
execute a hardware Reset by
software.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATMEGA8515L-8JUR | MCU AVR 8KB FLASH 8MHZ 44PLCC |
| ATMEGA8515L-8PJ | IC MCU AVR 8K 5V 8MHZ 40-DIP |
| ATMEGA8535-16JUR | MCU AVR 8K FLASH 16MHZ 44PLCC |
| ATMEGA8535L-8PJ | IC MCU AVR 8K 5V 8MHZ 40-DIP |
| ATMEGA88-15MT2 | MCU AVR 8K FLASH 15MHZ 32-QFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATmega649V-8MU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 64K FLASH 2K EE 4K SRAM ADC LCD RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA649V-8MUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 64KB FLSH 2KB EE 4KB SRAM LCD8MHz1.8V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA64A-AN | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA64A-ANR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA64A-AU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64K Flsh 2K EEPROM 4K SRAM 16MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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