參數(shù)資料
型號(hào)： ATF1504BE-5AX100
廠商： Atmel
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 64MC 1.8V 100-TQFP
標(biāo)準(zhǔn)包裝： 90
系列： ATF15xx
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 7.0ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 80
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤(pán)
配用： ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
13
3637B–PLD–1/08
ATF1504BE
6.
JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1504BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRE-
LOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504BE’s BSC can be fully described
using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1504BE testing to be
described and implemented using any one of the third-party development tools supporting this
standard.
The ATF1504BE also has the option of using the four JTAG-standard I/O pins for ISP. The
ATF1504BE is programmable through the four JTAG pins using the IEEE standard JTAG pro-
gramming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level
programming signals from the ISP interface for in-system programming. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
6.1
JTAG Boundary-scan Cell (BSC) Testing
The ATF1504BE contains 64 I/O pins and four dedicated input pins. Each input pin and I/O pin
has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in
detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one
for the macrocells. The BSCs in the device are chained together through the capture registers.
Input to the capture register chain is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active device data signals, to shift data in and
out of the device and to load data into the update registers. Control signals are generated inter-
nally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 6-1.
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note:
The ATF1504BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
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