參數(shù)資料
型號(hào)： ATF1504BE-5AX100
廠商： Atmel
文件頁(yè)數(shù)： 2/30頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 64MC 1.8V 100-TQFP
標(biāo)準(zhǔn)包裝： 90
系列： ATF15xx
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 7.0ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 80
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤(pán)
配用： ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
10
3637B–PLD–1/08
ATF1504BE
3.
Power Management
Unlike conventional CPLDs with sense amplifiers, the ATF1504BE is designed using low-power
full CMOS design techniques. This enables the ATF1504BE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1504BE also has an optional power-down mode. In this mode, current drops to below
100 A. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
4.
Security Feature
A fuse is provided to prevent unauthorized copying of the ATF1504BE fuse patterns. Once
enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature
remains accessible. To reset this feature, the entire memory array in the device must be erased.
5.
Programming Methods
The ATF1504BE devices are In-System Programmable (ISP) or In-System Configurable (ISC)
devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally
required for programming and facilitates rapid design iterations and field changes.
When using the ISP hardware or software to program the ATF1504BE devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for buried logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities. ATF1504BE devices can
also be programmed using standard third-party programmers. With a third-party programmer,
the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
The AT1504BE device supports several configuration modes which gives designers several
unique options for programming.
The different modes of programming are:
ISC – In-System Configuration
OTF – On-the-Fly Reconfiguration
DRA – Direct Reconfiguration Access
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