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參數(shù)資料
| 型號(hào)： | ATF1504ASVL-20QI100 |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 26/31頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 20NS LOWV LOWPWR 100QPFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | ATF15xx |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 64 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤(pán) |
| 其它名稱： | ATF1504ASVL20QI10 ATF1504ASVL20QI100 |
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ATF1504ASV(L)
1409J–PLD–6/05
Description
The ATF1504ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matri-
ces increase usable gate count and the odds of successful pin-locked design
modifications.
The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic func-
tions. The ATF1504ASV(L) contains four such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1504ASZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE CPLD |
| ATF1504ASZ-20AC100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE CPLD |
| ATF1504ASZ-20AC44 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE CPLD |
| ATF1504ASZ-20JC44 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE CPLD |
| ATF1504ASZ-20JC68 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE CPLD |
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