- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19822 > ATF1504ASV-15JU44 (Atmel)IC CPLD 15NS LOW VOLT 44PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | ATF1504ASV-15JU44 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 15NS LOW VOLT 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 64 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 608 (CN2011-ZH PDF) |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
16
ATF1504ASV(L)
1409J–PLD–6/05
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1504ASV(L). The boundary-scan technique involves the inclusion of a shift-
register stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to
support boundary-scan testing. The ATF1504ASV(L) does not currently include a Test
Reset (TRST) input pin because the TAP controller is automatically reset at power-up.
The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS,
IDCODE and HIGHZ. The ATF1504ASV(L)’s ISP can be fully described using JTAG’s
BSDL as described in IEEE Standard 1149.1b. This allows ATF1504ASV(L) program-
ming to be described and implemented using any one of the third-party development
tools supporting this standard.
The ATF1504ASV(L) has the option of using four JTAG-standard I/O pins for boundary-
scan testing (BST) and in-system programming (ISP) purposes. The ATF1504ASV(L) is
programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The JTAG feature is a programmable
option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are avail-
able as I/O pins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1504ASV(L) contains up to 68 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own bound-
ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the capture registers. Input to the capture register chain is fed in from the TDI pin while
the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration
for Input and I/O Pins
(Except JTAG TAP
Pins)
Note:
The ATF1504ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as
a design option.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GEM22DRTI | CONN EDGECARD 44POS DIP .156 SLD |
| 5-641285-1 | 21 CIR MTA 156 EDG CON F/T LF |
| VE-J43-CW-B1 | CONVERTER MOD DC/DC 24V 100W |
| RSA31DTMT | CONN EDGECARD 62POS R/A .125 SLD |
| EEM10DSEF-S243 | CONN EDGECARD 20POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1504ASV-15QC100 | 功能描述:IC CPLD 64 MACROCELL LV 100PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| ATF1504ASV-15QI100 | 功能描述:IC CPLD 15NS LOW VOL 100PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| ATF1504ASVL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Low-voltage, Complex Programmable Logic Device |
| ATF1504ASVL-15JC44 | 功能描述:IC CPLD 64 MACRO 15NS 44PLCC 制造商:microchip technology 系列:ATF15xx 包裝:管件 零件狀態(tài):停產(chǎn) 可編程類型:系統(tǒng)內(nèi)可編程（最少 10，000 次編程/擦除循環(huán)） 延遲時(shí)間 tpd（1）最大值:15.0ns 電源電壓 - 內(nèi)部:3 V ~ 3.6 V 宏單元數(shù):64 I/O 數(shù):32 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:44-LCC（J 形引線） 供應(yīng)商器件封裝:44-PLCC（16.59x16.59） 基本零件編號(hào):ATF1504 標(biāo)準(zhǔn)包裝:27 |
| ATF1504ASVL-20 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Low-voltage, Complex Programmable Logic Device |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。