參數(shù)資料
型號: ATF1504ASV-15JU44
廠商: Atmel
文件頁數(shù): 2/31頁
文件大?。?/td> 0K
描述: IC CPLD 15NS LOW VOLT 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 64
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC
包裝: 管件
產(chǎn)品目錄頁面: 608 (CN2011-ZH PDF)
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
10
ATF1504ASV(L)
1409J–PLD–6/05
Programming
ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for pro-
gramming and facilitates rapid design iterations and field changes.
Atm e l pro v id es I SP har d wa re a nd sof t war e t o allow pr ogr a mming of t h e
ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a com-
parable board tester or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504ASV(L) devices can also be programmed using standard third-party program-
mers. With third-party programmer the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1504ASV(L) has a special feature that locks the device and prevents the inputs
and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition the pin keeper
option preserves the former state during device programming, if this circuit were previ-
ously programmed on the device. This prevents disturbing the operation of other circuits
in the system while the ATF1504ASV(L) is being programmed via ISP.
All ATF1504ASV(L) devices are initially shipped in the erased state thereby making
them ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
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