- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364728 > ATC35 ATC35 Summary [Updated 1/03. 14 Pages] The ATC35 Cell-based ASIC (CBIC) family features a comprehensive library of 0.35-micron standard logic and I/O cells designed to operate with a supply voltage of 3.3V +/- 10% and memory cells compiled to the precise requirements of the design. It is fully compatible with Atmel＇s extensive range of microcontroller. DSP. memory. standard-interface. analog and application-specific cells. PDF資料下載
參數(shù)資料
| 型號(hào)： | ATC35 |
| 英文描述： | ATC35 Summary [Updated 1/03. 14 Pages] The ATC35 Cell-based ASIC (CBIC) family features a comprehensive library of 0.35-micron standard logic and I/O cells designed to operate with a supply voltage of 3.3V +/- 10% and memory cells compiled to the precise requirements of the design. It is fully compatible with Atmel＇s extensive range of microcontroller. DSP. memory. standard-interface. analog and application-specific cells. |
| 中文描述： | ATC35摘要[更新1 / 03。 14頁(yè)]的ATC35基于Cell的ASIC（CBIC）系列采用了綜合庫(kù)0.35微米標(biāo)準(zhǔn)邏輯和I / O設(shè)計(jì)工作在3.3V /供電電壓細(xì)胞- 10％和存儲(chǔ)單元編制的確切要求設(shè)計(jì)。它完全兼容Atmel的微控制器廣泛。數(shù)字信號(hào)處理器。內(nèi)存。標(biāo)準(zhǔn)接口。模擬和應(yīng)用程序特定的細(xì)胞。 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 109K |
| 代理商： | ATC35 |
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1
Features
Comprehensive Library of Standard Logic Cells
ATC35 I/O Cells Designed to Operate with V
DD
= 3.3V ± 0.3V as Main Target Operating
Conditions
IO35 Pad Library Provides Interface to 5V Environment
Oscillators and Phase Locked Loops for Stable Clock Sources
Memory Cells Compiled to the Precise Requirements of the Design
Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard Interface
and Application Specific Cells
High-Performance Analog Cells can be Developed on Request
Description
The Atmel ATC35 (AT56K) process is a proprietary 0.35 micron three-layer-metal
CMOS process intended for use with a supply voltage of 3.3V ± 0.3V. The following
table shows the range for which Atmel library cells have been characterized.
The Atmel cell libraries and megacell compilers have been designed in order to be
compatible with each other. Simulation representations exist for three types of operat-
ing conditions. They correspond to three characterization conditions defined as
follows:
MIN conditions:
T
J
= -55
°
C
V
DD
(cell) = 3.60V
Process = fast (industrial best case)
TYP conditions:
T
J
= +25
°
C
V
DD
(cell) = 3.30V
Process = typ (industrial typical case)
MAX conditions:
T
J
= +100
°
C
V
DD
(cell) = 3.00V
Process = slow (industrial worst case)
Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.
Output pad drain current corresponds to the output current of the pad when the output
voltage is V
OL
or V
OH
. The output resistor of the pad and the voltage drop due to
access resistors (in and out of the die) are taken into account. In order to have accu-
rate timing estimates, all characterization has been run on electrical netlists extracted
from the layout database.
Table 1.
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD3
DC Supply Voltage
Core and Standard I/Os
3.0
3.3
3.6
V
V
DD5
DC Supply Voltage
5V Interface I/Os
4.5
5.0
5.5
V
V
I
DC Input Voltage
0
V
DD
V
V
O
DC Output Voltage
0
V
DD
V
TEMP
Operating Free Air
Temperature Range
Industrial
-55
+85
°
C
Cell-based ASIC
ATC35
Summary
Rev. 1063CS–CBIC–01/03
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