參數(shù)資料
型號: AT91SAM7S32B-MU-999
廠商: Atmel
文件頁數(shù): 103/165頁
文件大?。?/td> 0K
描述: IC MCU ARM7 32KB FLASH 48-VQFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 3,500
系列: SAM7S
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 55MHz
連通性: I²C,SPI,SSC,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
42
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
11.2
ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents:
ARM Architecture Reference Manual (DDI 0100E)
ARM7TDMI Technical Reference Manual (DDI 0210B)
11.2.1
Instruction Type
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
11.2.2
Data Type
ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-
byte boundaries and half words to two-byte boundaries.
Unaligned data access behavior depends on which instruction is used where.
11.2.3
ARM7TDMI Operating Mode
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:
User: The normal ARM program execution state
FIQ: Designed to support high-speed data transfer or channel process
IRQ: Used for general-purpose interrupt handling
Supervisor: Protected mode for the operating system
Abort mode: Implements virtual memory and/or memory protection
System: A privileged user mode for the operating system
Undefined: Supports software emulation of hardware coprocessors
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are
entered in order to service interrupts or exceptions, or to access protected resources.
11.2.4
ARM7TDMI Registers
The ARM7TDMI processor has a total of 37registers:
31 general-purpose 32-bit registers
6 status registers
These registers are not accessible at the same time. The processor state and operating mode determine which
registers are available to the programmer.
At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception
processing.
Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current
instruction.
R14 holds the return address after a subroutine call.
R13 is used (by software convention) as a stack pointer.
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical regis-
ter in all processor modes. They are general-purpose registers, with no special uses managed by the architecture,
and can be used wherever an instruction allows a general-purpose register to be specified.
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