參數(shù)資料
型號: AT90USB647-MU
廠商: Atmel
文件頁數(shù): 51/106頁
文件大?。?/td> 0K
描述: IC AVR MCU 64K 64QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,300
系列: AVR®
應(yīng)用: USB 微控制器
核心處理器: AVR
程序存儲器類型: 閃存(64 kB)
控制器系列: AT90 USB
RAM 容量: 4K x 8
接口: 2 線串行,SPI 串行,USART,USB
輸入/輸出數(shù): 48
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
供應(yīng)商設(shè)備封裝: 64-VQFN(9x9)
配用: ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB647-16MU
AT90USB647-16MU-ND
Q4939729A
49
7593L–AVR–09/12
AT90USB64/128
7.10
PLL
The PLL is used to generate internal high frequency (48MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1). The internal RC oscillator can not be used for USB operations.
7.10.1
Internal PLL for USB interface
The internal PLL in Atmel AT90USB64/128 generates a clock frequency that is 24× multiplied
from nominally 2MHz input. The source of the 2MHz PLL input clock is the output of the internal
PLL clock prescaler that generates the 2MHz (see Section 7.10.2 for PLL interface).
Figure 7-4.
PLL clocking system.
7.10.2
PLLCSR – PLL Control and Status Register
Bit 7..5 – Res: Reserved bits
These bits are reserved bits in the AT90USB64/128 and always read as zero.
Bit 4..2 – PLLP2:0 PLL prescaler
These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the
PLL.
11
01
Reserved
11
10
Reserved
11
Reserved
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock division factor
8MHz
RC OSCILLATOR
XTAL1
XTAL2
OSCILLATORS
PLL
24x
PLLE
Lock
detector
PLOCK
clkUSB
System clock
clk
2MHz
PLL clock
prescaler
(48MHz)
Bit
7
6
5432
10
$29 ($29)
PLLP2
PLLP1
PLLP0
PLLE
PLOCK
PLLCSR
Read/write
R
R/W
Initial value
0
0000
0/1
0
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