參數(shù)資料
型號: AT90USB647-MU
廠商: Atmel
文件頁數(shù): 16/106頁
文件大?。?/td> 0K
描述: IC AVR MCU 64K 64QFN
產品培訓模塊: megaAVR Introduction
標準包裝: 1,300
系列: AVR®
應用: USB 微控制器
核心處理器: AVR
程序存儲器類型: 閃存(64 kB)
控制器系列: AT90 USB
RAM 容量: 4K x 8
接口: 2 線串行,SPI 串行,USART,USB
輸入/輸出數(shù): 48
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
供應商設備封裝: 64-VQFN(9x9)
配用: ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB647-16MU
AT90USB647-16MU-ND
Q4939729A
17
7593L–AVR–09/12
AT90USB64/128
Figure 5-6.
Single cycle ALU operation.
5.8
Reset and interrupt handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory program-
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 68 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Total execution time
Register operands fetch
ALU operation execute
Result write back
T1
T2
T3
T4
clk
CPU
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