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| 型號： | AT90S8535-8JI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 78/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K 8MHZ A/D IT 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | AVR® 90S |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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PIC16C71X
DS30272A-page 54
1997 Microchip Technology Inc.
8.4.5
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator conguration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 8-11,
and
depict
time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 8-12). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Table 8-10 and Table 8-11 show the reset conditions for
some special function registers, while Table 8-12 and
Table 8-13 show the reset conditions for all the
registers.
8.4.6
POWER CONTROL/STATUS REGISTER
(PCON)
The Power Control/Status Register, PCON has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Conguration Word).
Applicable Devices
710 71 711 715
Applicable Devices
710 71 711 715
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
For the PIC16C715, bit2 is PER (Parity Error Reset). It
is cleared on a Parity Error Reset and must be set by
user software. It will also be set on a Power-on Reset.
For the PIC16C715, bit7 is MPEEN (Memory Parity
Error Enable). This bit reects the status of the MPEEN
bit in conguration word. It is unaffected by any reset of
interrupt.
8.4.7
PARITY ERROR RESET (PER)
The PIC16C715 has on-chip parity bits that can be
used to verify the contents of program memory. Parity
bits may be useful in applications in order to increase
overall reliability of a system.
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
a program executes, the parity is veried. The even par-
ity bit is XOR’d with the even bits in the program mem-
ory word. The odd parity bit is negated and XOR’d with
the odd bits in the program memory word. When an
error is detected, a reset is generated and the PER ag
bit 2 in the PCON register is cleared (logic ‘0’). This indi-
cation can allow software to act on a failure. However,
there is no indication of the program memory location
of the failure in Program Memory. This ag can only be
set (logic ‘1’) by software.
The parity array is user selectable during programming.
Bit 7 of the conguration word located at address
2007h can be programmed (read as ‘0’) to disable par-
ity. If left unprogrammed (read as ‘1’), parity is enabled.
Applicable Devices
710 71 711 715
TABLE 8-5:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C71
TABLE 8-6:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715
Oscillator Conguration
Power-up
Wake-up from SLEEP
PWRTE = 1
PWRTE = 0
XT, HS, LP
72 ms + 1024TOSC
1024TOSC
1024 TOSC
RC
72 ms
—
Oscillator Conguration
Power-up
Brown-out
Wake-up from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
1024TOSC
72 ms + 1024TOSC
1024TOSC
RC
72 ms
—
72 ms
—
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