參數(shù)資料
型號： AT90S8535-8JI
廠商： Atmel
文件頁數(shù)： 63/127頁
文件大?。?/td> 0K
描述： IC MCU 8K 8MHZ A/D IT 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 8KB（4K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
PIC16C71X
DS30272A-page 40
1997 Microchip Technology Inc.
7.1
A/D Acquisition Requirements
For the A/D converter to meet its specied accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 7-5. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 k
. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, Equation 7-
1 may be used. This equation calculates the acquisition
time to within 1/2 LSb error is used (512 steps for the
A/D). The 1/2 LSb error is the maximum error allowed
for the A/D to meet its specied accuracy.
EQUATION 7-1:
A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) (1 - e(-T
CAP
/CHOLD(RIC + RSS + RS)))
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
The above equation reduces to:
TCAP = -(51.2 pF)(1 k
+ RSS + RS) ln(1/511)
Example 7-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
CHOLD = 51.2 pF
Rs = 10 k
1/2 LSb error
VDD = 5V
→ Rss = 7 k
Temp (application system max.) = 50
°C
VHOLD = 0 @ t = 0
EXAMPLE 7-1:
CALCULATING THE
MINIMUM REQUIRED
AQUISITION TIME
TACQ = Amplier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefcient
TACQ = 5
s + TCAP + [(Temp - 25°C)(0.05 s/°C)]
TCAP = -CHOLD (RIC + RSS + RS) ln(1/511)
-51.2 pF (1 k
+ 7 k + 10 k) ln(0.0020)
-51.2 pF (18 k
) ln(0.0020)
-0.921
s (-6.2364)
5.747
s
TACQ = 5
s + 5.747 s + [(50°C - 25°C)(0.05 s/°C)]
10.747
s + 1.25 s
11.997
s
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 k
. This is
required to meet the pin leakage speci-
cation.
Note 4: After a conversion has completed, a
2.0TAD delay must complete before acqui-
sition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
FIGURE 7-5:
ANALOG INPUT MODEL
CPIN
VA
Rs
ANx
5 pF
VDD
VT = 0.6V
I leakage
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 10 11
( k
)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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