參數(shù)資料
型號: AT90S2313-10PC
廠商: Atmel
文件頁數(shù): 18/92頁
文件大小: 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
25
AT90S2313
0839I–AVR–06/02
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always reads as zero.
Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(T i m er/ C ounte r0 O v e rf l o w Int errupt En a b l e ) a n d T O V 0 a re s et (one), t he
Timer/Counter0 Overflow Interrupt is executed.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2313 and always reads as zero.
External Interrupts
The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The External Interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the External Interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
The External Interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles,
minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector
address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter (two bytes) is pushed onto the Stack, and the Stack
Pointer is decremented by two. The Power-down is normally a relative jump to the inter-
rupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution
of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack
Pointer is incremented by two, and the I-flag in SREG is set. When the AVR exits from
an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
Bit
7654
3210
$35 ($55)
SE
SM
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R
R/W
Initial value
0000
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