參數(shù)資料
型號(hào): AT90S2313-10PC
廠商: Atmel
文件頁(yè)數(shù): 11/92頁(yè)
文件大?。?/td> 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
19
AT90S2313
0839I–AVR–06/02
Reset Sources
The AT90S2313 has three sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT).
External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
During Reset, all I/O Registers are then set to their initial values, and the program starts
execution from address $000. The instruction placed in address $000 must be an RJMP
(Relative Jump) instruction to the reset handling routine. If the program never enables
an interrupt source, the Interrupt Vectors are not used, and regular program code can
be placed at these locations. The circuit diagram in Figure 23 shows the reset logic.
Table 3 defines the timing and electrical parameters of the reset circuitry.
Figure 23. Reset Logic
Note:
1. The Power-on Reset will not work unless the supply voltage has been below VPOT
(falling).
The user can select the start-up time according to typical Oscillator start-up. The num-
ber of WDT Oscillator cycles used for each time-out is shown in Table 4. The frequency
of the Watchdog Oscillator is voltage-dependent, as shown in “Typical Characteristics”
Table 3. Reset Characteristics (VCC =5.0V)
Symbol
Parameter
Min
Typ
Max
Units
V
POT
Power-on Reset Threshold Voltage (rising)
1.0
1.4
1.8
V
Power-on Reset Threshold Voltage (falling)
0.4
0.6
0.8
V
VRST
RESET Pin Threshold Voltage
0.85 VCC
V
t
TOUT
Reset Delay Time-out Period
FSTRT Unprogrammed
11.0
16.0
21.0
ms
tTOUT
Reset Delay Time-out Period
FSTRT Programmed
0.25
0.28
0.31
ms
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