參數(shù)資料
型號: AT7601FG
廠商: AME, Inc.
英文描述: Printer Port Controller
中文描述: 打印機(jī)端口控制器
文件頁數(shù): 9/35頁
文件大?。?/td> 195K
代理商: AT7601FG
AME, Inc.
9
AT7601F
Printer Port Controller
Rev. B.02
5-2-4 EPP Data Port 0 ~ 3
These four registers are available only in EPP mode. Bit definitions of each port are as follows:
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and
output to the ports PD0-PD7 during a write operation. The leading edge of LOW latches the data for the
duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of LOR causes an EPP read cycle
to be performed and the data to be output to the host CPU.
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
7
5
6
4
3
2
1
0
REGISTER
7
6
5
4
3
2
1
0
Data Port
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Status Port
BUSY#
ACK#
PE
SLCT
ERR#
1
1
TMout
Control Port
1
1
PDIR
IRQEn
SLIN
INIT#
AFD
STB
EPP Address
Port
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data
Port 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data
Port 1
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data
Port 2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
EPP Data
Port 3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Table 7. Parallel Port and EPP Registers
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