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參數(shù)資料
| 型號： | AT7601FG |
| 廠商： | AME, Inc. |
| 英文描述： | Printer Port Controller |
| 中文描述： | 打印機端口控制器 |
| 文件頁數(shù)： | 18/35頁 |
| 文件大?。?/td> | 195K |
| 代理商： | AT7601FG |
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AME, Inc.
18
Printer Port Cotroller
AT7601F
Rev. B.02
Bit 4
ErrIntrEn# : Read/Write (Valid only in ECP Mode)
1 Disables the interrupt generated on the asserting edge of Fault#.
0 Enables an interrupt pulse on the high to low edge of Fault#. Note that an interrupt will be generated if
Fault# is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being
lost in the time between the read of the ECR and the write of the ECR.
Bit 3 DMAEn
Read/Write
1 Enables DMA (DMA starts when Servicelntr is 0).
0 Disables DMA unconditionally.
Bit 2 Servicelntr
Read/Write
Disables DMA and all of the service interrupts.
Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred
Servicelntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts.
Writing this bit to a 1 will not cause an interrupt.
Case DMAEn=1
During DMA (this bit is set to a 1 when terminal count is reached).
Case DMAEn=0 direction=0
This bit shall be set to 1 whenever there are WriteIntrThreshold or more bytes free in the FIFO.
Case DMAEn=0 direction=1
This bit shall be set to 1 whenever there are ReadlntrThreshold or more valid bytes to be read from the
FIFO.
Bit 1 full
Read only
1 The FIFO cannot accept another byte or the FIFO is completely full.
0 The FIFO has at least 1 free byte.
Bit 0 empty
Read only
1 The FIFO is completely empty.
0 The FIFO contains at least 1 byte of data.
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