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參數(shù)資料
| 型號(hào)： | AT7601FG |
| 廠商： | AME, Inc. |
| 英文描述： | Printer Port Controller |
| 中文描述： | 打印機(jī)端口控制器 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 195K |
| 代理商： | AT7601FG |
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AME, Inc.
10
Printer Port Cotroller
AT7601F
Rev. B.02
5-2-5 EPP 1.9 Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are
also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the
standard or bi-directional mode, and all output signals (STB, AFDD, INIT) are as set by the SPP Control
Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (IOR# or IOW# asserted ) to WAIT# being deasserted (after command). If
a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit
0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to
always be in a write mode and the WRITE# signal to always be asserted.
5-2-6 EPP Version 1.7 Operation
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in
the standard or bi-directional mode, and all output signals (STB, AFD, INIT) are as set by the SPP
Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from
the start of the EPP cycle (IOR# or IOW# asserted) to the end of the cycle IOR# or IOW# deasserted). If
a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit
0.
5-3 Extended Capabilities Parallel (ECP) Port
ECP provides a number of advantages, some of which are listed below. The individual features are explained
in greater detail in the remainder of this section.
l
High performance half-duplex forward and reverse channel
l
Interlocked handshake, for fast reliable transfer
l
Optional single byte RLE compression for improved throughput(64:1)
l
Channel addressing for low-cost peripherals
l
Maintains link and data layer separation
l
Permits the use of active output drivers
l
Permits the use of adaptive signal timing
l
Peer-to-peer capability
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