參數(shù)資料
型號(hào): AT43USB355E-AU
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
中文描述: 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64
文件頁數(shù): 77/115頁
文件大小: 610K
代理商: AT43USB355E-AU
77
AT43USB355
2603G–USB–04/06
No-data Status
Response State
The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero
length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE
interrupt.
Control Read Data
Response State
The Function Interface Unit receives an IN token from the Host. The FIU responds with NAKs
until TX_PACKET_READY is set. The FIU then sends the data in the FIFO upstream, retrying
until it successfully receives an ACK from the host. Finally, the FIU clears the
TX_PACKET_READY bit and asserts a TX_COMPLETE interrupt.
Hardware
Firmware
1.
IN token from Host
2.
Send DATA1(0)
3.
ACK from Host
Set TX COMPLETE
INT
4.
5.
Read UISR
6.
Read CSR0
7.
If SET ADDRESS, program the new
Address, set ADD_EN bit
Clear TX_COMPLETE, clear Data
End, set Force STALL in CAR0
Set UIAR[EP0 INTACK]
8.
9.
Hardware
Firmware
1.
IN token from Host
2.
a. If TX Packet Ready = 1, send
DATA0/DATA1
b. If TX Packet Ready = 0, send NAK
ACK from Host
3.
4.
Clear TX Packet Ready
Set TX Complete
INT
5.
Read UISR
6.
Read CSR0
7.
Clear TX COMPLETE in CAR0:
a. If more data: fill FIFO, set TX
Packet Ready, set DIR in CAR0
b. If no more data: set Force STALL,
set DATA END in CAR0
Set UIAR[EP0 INTACK] to clear
interrupt source
8.
Repeat steps 1 through 8
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