
AT43312A
8
An IN Token packet from the Host to Endpoint 1 indicates
a request for port change status. If the Hub has not
detected any change on its ports, or any changes in itself,
then all bits in this register will be 0 and the Hub Controller
will return a NAK to requests on Endpoint1. If any of bits
0-4 is 1, the Hub Controller will transfer the whole byte. The
Hub Controller will continue to report a status change when
polled until that particular change has been removed by a
ClearPortFeature request from the Host. No status change
will be reported by Endpoint 1 until the AT43312A has been
enumerated and configured by the Host via Endpoint 0.
Oscillator and Phase-Locked-Loop
All the clock signals required to run the AT43311 is derived
from an on-chip oscillator. To reduce EMI and power dissi-
pation in the system, the oscillator is designed to operate
with a 6 MHz crystal. An on-chip PLL generates the high
frequency for the clock/data separator of the Serial Inter-
face Engine. In the suspended state, the oscillator circuitry
is turned off. To assure quick startup, a crystal with a high
Q, or low ESR, should be used. To meet the USB hub fre-
quency accuracy and stability requirements for hubs, the
crystal should have an accuracy and stability of better than
100 PPM. Even though the oscillator circuit would work
with a ceramic resonator, its use is not recommended
because a resonator would not have the frequency accu-
racy and stability.
A 6 MHz series resonance quartz crystal with a load capac-
itance of approximately 10 pF is recommended. The
oscillator is a special low-power design and in most cases
no external capacitors and resistors are necessary. If the
crystal used cannot tolerate the drive levels of the oscilla-
tor, a series resistor between OSC2 and the crystal pin is
recommended.
The clock can also be externally sourced. In this case, con-
nect the clock source to the OSC1 pin, while leaving OSC2
pin floating. The switching level at the OSC1 pin can be as
low as 0.47V (see Table 8) and a CMOS device is required
to drive this pin to maintain good noise margins at the low
switching level.
Figure 4.
Oscillator and PLL Connections
For proper operation of the PLL, an external RC filter con-
sisting of a series RC network of 100
and 10 nF in parallel
with a 2 nF capacitor must be connected from the LFT pin
to VSS.
To provide the best operating condition for the AT43312A,
careful consideration of the power supply connections are
recommended. Use short, low-impedance connections to
all power supply lines: VCC5, and VSS. Use sufficient
decoupling capacitors to reduce noise: 0.1 μF decoupling
capacitors of high quality, soldered as close as possible to
the package pins are recommended.
Table 4.
Status Change Register
Bit
Function
Value
Meaning
0
Hub status change
0
1
No change in status
Change in status detected
1
Port1 status change
0
1
No change in status
Change in status detected
2
Port2 status change
0
1
No change in status
Change in status detected
3
Port3 status change
0
1
No change in status
Change in status detected
4
Port4 status change
0
1
No change in status
Change in status detected
5-7
Reserved
000
Default values
AT43312A
OSC1
OSC2
LFT
Y1
6.000 MHz
R1
100
C1
10nF
C2
2nF
U1