參數(shù)資料
型號: AT43312A
廠商: Atmel Corp.
英文描述: Self- and Bus-powered USB Hub Controller(自供電和總線供電USB集線器控制器)
中文描述: 自和總線供電的USB集線器控制器(自供電和總線供電的USB集線器控制器)
文件頁數(shù): 3/18頁
文件大?。?/td> 249K
代理商: AT43312A
AT43312A
3
Signal Description
OSC1
Oscillator Input. Input to the inverting 6 MHz oscillator
amplifier.
OSC2
Oscillator Output. Output of the inverting oscillator
amplifier.
LFT
PLL Filter. For proper operation of the PLL, this pin should
be connected through a 2.2 nF capacitor in parallel with a
100
resistor in series with a 10 nF capacitor to ground
(VSS).
SELF/BUS
Hub Power Mode. Input signal that sets the bus or self-
powered mode operation. A high on this pin enables the
self-powered mode, a low enables the bus-powered mode.
LPSTAT
Local Power Status. In the self-powered mode, this is an
input pin that should be connected to the local power sup-
ply through a 47k
resistor. The voltage on this pin is used
by the chip for reporting the condition of the local power
supply. In the bus-powered mode, this pin is not used.
DP0
Upstream Plus USB I/O. This pin should be connected to
CEXT through an external 1.5k
pull-up resistor. DP0 and
DM0 form the differential signal pin pairs connected to the
Host Controller or an upstream Hub.
DM0
Upstream Minus USB I/O.
DP[1:4]
Port Plus USB I/O. This pin should be connected to VSS
through an external 15k
resistor. DP[1:4] and DM[1:4] are
the differential signal pin pairs to connect downstream USB
devices.
DM[1:4]
Port Minus USB I/O. This pin should be connected to VSS
through an external 15k
resistor
Table 2.
32-pin LQFP Assignment
Pin
Signal
Type
1
DP3
B
2
DM4
B
3
DP4
B
4
PWR1
O
5
PWR2
O
6
PWR3
O
7
PWR4
O
8
VCC5
V
9
VSS
V
10
OSC1
I
11
OSC2
O
12
LFT
I
13
TEST
I
14
OVC4
I
15
OVC3
I
16
OVC2
I
17
OVC1
I
18
LPSTAT
I
19
SELF/BUS
I
20
STAT4
O
21
STAT3
O
22
STAT2
O
23
STAT1
O
24
DMO
B
25
DP0
B
26
DM1
B
27
DP1
B
28
CEXT
O
29
DM2
B
30
DP2
B
31
VSS
V
32
DM3
B
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