參數(shù)資料
型號: AT43312A
廠商: Atmel Corp.
英文描述: Self- and Bus-powered USB Hub Controller(自供電和總線供電USB集線器控制器)
中文描述: 自和總線供電的USB集線器控制器(自供電和總線供電的USB集線器控制器)
文件頁數(shù): 4/18頁
文件大?。?/td> 249K
代理商: AT43312A
AT43312A
4
OVC[1:4]
Overcurrent. This is the input signal used to indicate to the
AT43312A that an overcurrent is detected at the port. If
OVCx is asserted, AT43312A will assert the PWRx pin and
report the status to the USB Host.
PWR[1:4]
Power Switch. This is an output signal used to enable or
disable the external voltage regulator supplying power to a
port. PWRx is de-asserted when a power supply problem is
detected at OVCx.
STAT[1:4]
Connect Status. This is an output pin indicating that a port
is properly connected. STATx is asserted when the port is
enabled.
CEXT
External Capacitor. For proper operation of the on chip reg-
ulator, a 0.27 μF capacitor must be connected to this pin.
TEST
Test. This pin should be connected to a logic high for nor-
mal operation.
VCC
5V Power Supply.
VSS
Ground.
Functional Description
Summary
The Atmel AT43312A is a USB hub controller for use in a
standalone hub as well as an add-on hub for an existing
non-USB peripheral such a PC display monitor or key-
board. In addition to supporting the standard USB hub
functionality, the AT43312A has additional features to
enhance the user friendliness of the hub.
USB Ports
The AT43312A’s upstream port, Port0, is a full-speed port.
A 1.5k
pull-up resistor to the 3.3V regulator output, CEXT,
is required for proper operation. The downstream ports
support both full-speed as well as low-speed devices. 15k
pull-down resistors are required at their inputs.
Full-speed signal requirements demand controlled
rise/fall times and impedance matching of the USB ports.
To meet these requirements, 22
resistors must be
inserted in series between the USB data pins and the USB
connectors.
Hub Repeater
The Hub Repeater is responsible for port connectivity setup
and tear-down. It also supports exception handling such as
bus fault detection and recovery, and connect/disconnect
detection. Port0 is the root port and is connected to the root
hub or an upstream hub. When a packet is received at
Port0, the AT43312A propagates it to all the enabled down-
stream ports. Conversely, a packet from a downstream port
is transmitted from Port0.
The AT43312A supports downstream port data signaling at
both 1.5 Mb/s and 12 Mb/s. Devices attached to the down-
stream ports are determined to be either full-speed or low-
speed depending which data line (DP or DM) is pulled high.
If a port is enumerated as low-speed, its output buffers
operate at a slew rate of 75-300 ns, and the AT43312A will
not propagate any traffic to that port unless it is prefaced
with a preamble PID. Low-speed data following the pream-
ble PID is propagated to both low- and full-speed devices.
The AT43312A will enable low-speed drivers within four
full-speed bit times of the last bit of a preamble PID, and
will disable them at the end of an EOP. Packets out of
Port0 are always transmitted using the full-speed drivers.
All the AT43312A ports independently drive and monitor
their DP and DM pins so that they are able to detect and
generate the “J”, “K”, and SE0 bus signaling states. Each
hub port has single-ended and differential receivers on its
DP and DM lines. The port I/O buffers comply with the volt-
age levels and drive requirements as specified in the USB
Specifications Rev 1.0.
The Hub Repeater implements a frame timer which is timed
by the 12 MHz USB clock and gets reset every time an
SOF token is received from the Host.
Serial Interface Engine
The Serial Interface Engine handles the USB communica-
tion protocol. It performs the USB clock/data separation,
the NRZI data encoding/decoding, bit stuffing, CRC gener-
ation and checking, USB packet ID decoding and
generation, and data serialization and de-serialization. The
on chip phase locked loop generates the high frequency
clock for the clock/data separation circuit.
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