參數(shù)資料
型號： AT32UC3L064-ZAUR
廠商： Atmel
文件頁數(shù)： 11/174頁
文件大?。?/td> 0K
描述： IC MCU AVR32 64K FLASH 48VQFN
產(chǎn)品培訓(xùn)模塊： AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝： 1
系列： AVR®32 UC3 L
核心處理器： AVR
芯體尺寸： 32-位
速度： 50MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-VFQFN 裸露焊盤
包裝： 剪切帶 (CT)
其它名稱： AT32UC3L064-ZAURCT
108
32099I–01/2012
AT32UC3L016/32/64
9.5.4.1
Operation example
Figure 9-2 shows a typical memory map, consisting of some memories, some simple peripher-
als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has
been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no
way of accessing for example the Transmit Holding register in the UART, present on address X
on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be
accessed. If for example RTR0 is configured to point to address X, an access to RTR0 will be
remapped by the SAU to address X according to the algorithm presented above. By program-
ming the SAU RTRs, specific addresses in modules that have generally been protected by the
MPU can be performed.
Figure 9-2.
Example Memory Map for a System with SAU
9.5.5
Interrupts
The SAU can generate an interrupt request to signal different events. All events that can gener-
ate an interrupt request have dedicated bits in the Status Register (SR). An interrupt request will
be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are
set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared
by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in SR is cleared by writing a one to the corre-
sponding bit in the Interrupt Clear Register (ICR).
The following SR bits are used for signalling the result of SAU accesses:
RTR Address Error (RTRADR) is set if an illegal address is written to the RTRs. Only
addresses in the range 0xFFFC0000-0xFFFFFFFF are allowed.
Master Interface Bus Error (MBERROR) is set if any of the conditions listed in Section 9.5.7
occurred.
Transmit Holding
Baudrate
Control
Receive Holding
Channel 1
RTR0
RTR1
Address X
Address Z
UART
SAU
CONFIG
SAU
CHANNEL
UR
RTR62
..
.
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