
AT29BV010A
2
To allow for simple in-system reprogrammability, the
AT29BV010A does not require high input voltages for pro-
gramming. The device can be operated with a single 2.7V
to 3.6V supply. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the
AT29BV010A is performed on a sector basis; 128 bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 128
bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and
then program the latched data using an internal control
timer. The end of a program cycle can be detected by
DATA polling of I/O7. Once the end of a program cycle has
been detected, a new access for a read or program can
begin.
Block Diagram
Device Operation
READ:
The AT29BV010A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
SOFTWARE DATA PROTECTION PROGRAMMING:
The
AT29BV010A has 1024 individual sectors, each 128 bytes.
Using the software data protection feature, byte loads are
used to enter the 128 bytes of a sector to be programmed.
The AT29BV010A can only be programmed or repro-
grammed using the software data protection feature. The
device is programmed on a sector basis. If a byte of data
within the sector is to be changed, data for the entire 128-
byte sector must be loaded into the device. The data in any
byte that is not loaded during the programming of its sector
will be indeterminate. The AT29BV010A automatically
does a sector erase prior to loading the data into the sector.
An erase command is not required.
Software data protection protects the device from inadvert-
ent programming. A series of three program commands to
specific addresses with specific data must be presented to
the device before programming may occur. The same three
program commands must begin each program operation.
All software program commands must obey the sector pro-
gram timing specifications. Power transitions will not reset
the software data protection feature, however the software
feature will guard against inadvertent program cycles dur-
ing power transitions.
Any attempt to write to the device without the 3-byte com-
mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
t
WC
, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 128 bytes of data must be loaded into each sector. Any
byte that is not loaded during the programming of its sector
will be indeterminate. Once the bytes of a sector are loaded
into the device, they are simultaneously programmed dur-
ing the internal programming period. After the first data
byte has been loaded into the device, successive bytes are
entered in the same manner. Each new byte to be pro-
grammed must have its high to low transition on WE (or
CE) within 150
μ
s of the low to high transition of WE (or
CE) of the preceding byte. If a high to low transition is not
detected within 150
μ
s of the last low to high transition, the
load period will end and the internal programming period
will start. A7 to A16 specify the sector address. The sector
address must be valid during each high to low transition of
WE (or CE). A0 to A6 specify the byte address within the
sector. The bytes may be loaded in any order; sequential
loading is not required.
HARDWARE DATA PROTECTION:
protect against inadvertent programs to the AT29BV010A
in the following ways: (a) V
CC
sense—if V
CC
is below 2.0V
(typical), the program function is inhibited; (b) V
CC
power on
delay—once V
CC
has reached the V
CC
sense level, the
device will automatically time out 10 ms (typical) before
programming; (c) Program inhibit—holding any one of OE
low, CE high or WE high inhibits program cycles; and (d)
Noise filter— pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
INPUT LEVELS:
While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs
(
OE,
CE and WE) may be driven from 0 to 5.5V without
Hardware features