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參數(shù)資料
| 型號： | AT25320 |
| 廠商： | Atmel Corp. |
| 英文描述： | 32K SPI Serial EEPROMs(32K SPI串行EEPROM) |
| 中文描述： | 32K的的SPI（32K的的SPI串行EEPROM的串行EEPROM） |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 250K |
| 代理商： | AT25320 |
AT25080/160/320/640
6
Serial Interface Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an
input, the AT25080/160/320/640 always operates as a
slave.
TRANSMITTER/RECEIVER:
The AT25080/160/320/640
has separate pins designated for data transmission (SO)
and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit trans-
mitted and received.
SERIAL OP-CODE:
After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no
data will be shifted into the AT25080/160/320/640, and the
serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reini-
tialize the serial communication.
CHIP SELECT:
The AT25080/160/320/640 is selected
when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the serial out-
put pin (SO) will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS
pin to select the AT25080/160/320/640. When the device is
selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master
device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is
“
1
”
, all write
operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initi-
ated, WP going low will have no effect on any write opera-
tion to the status register. The WP pin function is blocked
when the WPEN bit in the status register is "0". This will
allow the user to install the AT25080/160/320/640 in a sys-
tem with the WP pin tied to ground and still be able to write
to the status register. All WP pin functions are enabled
when the WPEN bit is set to
“
1
”
.
SPI Serial Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT25F1024AN-10SU-2.7 | SPI Serial Memory |
| AT25F1024AY4-10YU-2.7 | SPI Serial Memory |
| AT25F1024A | High Speed CMOS Logic Hex Buffers/Line Drivers with Inverting 3-State Outputs 16-PDIP -55 to 125 |
| AT25F1024 | High Speed CMOS Logic Hex Buffers/Line Drivers with Non-Inverting 3-State Outputs 16-SOIC -55 to 125 |
| AT25F512 | SPI Serial Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT25320-10PA-2.7C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|4KX8|CMOS|DIP|8PIN|PLASTIC |
| AT25320-10PA-5.0C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|4KX8|CMOS|DIP|8PIN|PLASTIC |
| AT25320-10PC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25320-10PC-1.8 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
| AT25320-10PC-2.7 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:SPI Serial EEPROMs |
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