參數(shù)資料
型號(hào)： AT24RF08C
廠商： Atmel Corp.
英文描述： Asset Identification EEPROM(雙存取EEPROM（帶一個(gè)有線串行端口和一個(gè)無(wú)線RFID端口）)
中文描述： 資產(chǎn)識(shí)別的EEPROM（雙存取的EEPROM（帶一個(gè)有線串行端口和一個(gè)無(wú)線RFID的端口））
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 429K
代理商： AT24RF08C
AT24RF08C
9
Both the BL and PL registers used in the read and write
commands to determine the address are set to 0 upon
power-up. The PL value is automatically set to the transmit-
ted value when the Write Page and/or Read Page
commands are executed.
The
“
Set BL to ID
”
command permits the ID page (page 1)
to be written from the RFID port if the lock bit is set to a
one. This lock bit is the 121st bit sent as part of a write
page command or the 25th bit sent as part of a write word 3
command. The first 96 bits of this page are the ID bits
which are transmitted by the chip in the same order as they
are written.
The PL register value is ignored when the BL points to the
ID page. Also, the page number is ignored on page write
commands.
Listening Window Structure
After any header, ID or data element is read from the
device (for any reason) the chip delays further
transmissions for a period of time to determine if the reader
intends to communicate with the tag. The length of the
various delays and the actions that the device takes during
this delay depends on the current state of the device and/or
any command issued by the reader.
In general, the tag expects to see communications from the
reader start between the middle of the first bit time and the
end of the second time (256 μs to 1024 μs) after the end of
the previous communication. The beginning of the first and
the entire third write bit times are ignored in order to
prevent the tag from erroneously seeing its own modulation
as incoming from the reader. Specific timing requirements
for these communications are shown in the RFID
Acknowledge timing diagram and the RFID
Command/Data Timing Diagram on page 16.
There are four states possible for tags that are sufficiently
in the field for the internal voltage to be above the reset
level. They are listed below and shown in bold throughout
this document.
Init
Upon power up, and after execution of the global reset
quiet bit command, all chips are in this state. Chips that do
not have their
QUIET
bit set also go into this state after the
execution of a Disable/Set Quiet command. While in this
state, chips delay a random length of time and then
transmit their 4-bit header. Tags in this state honor all
global commands except those that start during the period
in which they are transmitting their header and during the
first 512 μs of the listening window. They transition to
Unselected
after global command execution, other than
global reset quiet which stays in init.
Selected
If the reader issues an acknowledge pulse to a tag in the
init
state during the second write bit time after the header is
transmitted, then the tag is
selected
and it will repeatedly
transmit its ID until the reader sends a command to the tag.
The tag remains
selected
through the entire sequence of
ID transmission and subsequent command execution
unless there is a fault of some kind.
Unselected
If a tag in the
init
state senses modulation interval greater
than 32 μs in length during any bit time other than the
second then it moves into the
unselected
state, and
remains that way until it sees a Disable Chip command.
Unselected
tags also honor the three global commands
while they are
“
waiting
”
. All other commands are ignored.
Quiet
When in the
quiet
state, the chip does not activate its
modulation resistor at any time. Only the three global
commands will be honored by the chip. All other
commands are ignored.
The following paragraphs describe five kinds of delays that
are possible.
Random
The chip delays a pseudo random length of time. The
length of this delay sequences through the following
number of read bit times (128 μs each): 64, 48, 24, 32, 56,
40 and 72. The starting point among this list is based on
the first three bits of byte 0 of the ID page within the
EEPROM. If these bits are 111, then the sequence above
will be preceded by a 16-bit delay. The minimum and
maximum delays are 2048 μs and 9216 μs, respectively.
Three Bit
The device waits for three write bit times and then one read
bit time (for a total of 1664 μs) before retransmitting the
data that was just transmitted. During the t
CDM1
interval, the
reader may issue a command to the chip. See
“
RFID
Command/Data Timing
”
on page 16.
Long
After certain commands,
selected
chips wait indefinitely for
the next command from the reader. This command should
start during the t
CDM1
interval after the end of the command
transmission.
Infinite
Unselected
chips wait in this state for any of the three
global commands or the Disable Chip command. If no legal
command transmission ever occurs, then the device will
stay in this delay loop for as long as power is applied from
the RFID port.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT24RF08CN-105C 功能描述:IC EEPROM 8KBIT 100KHZ 8SOIC 制造商:microchip technology 系列:- 包裝:管件 零件狀態(tài):停產(chǎn) 存儲(chǔ)器類型:非易失 存儲(chǔ)器格式:EEPROM 技術(shù):EEPROM 存儲(chǔ)容量:8Kb （1K x 8） 時(shí)鐘頻率:100kHz 寫周期時(shí)間 - 字，頁(yè):10ms 訪問時(shí)間:450ns 存儲(chǔ)器接口:I2C 電壓 - 電源:2.4 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TJ） 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SOIC 基本零件編號(hào):AT24RF08 標(biāo)準(zhǔn)包裝:1
AT24RF08CN-10SC 功能描述:電可擦除可編程只讀存儲(chǔ)器 RFID 8k RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
AT24RF08CN10SC-C0006 制造商:Atmel Corporation 功能描述:EEPROM
AT24RF08CT-10T1C 制造商:Atmel Corporation 功能描述:1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14
AT24RF08-EK 功能描述:KIT EVAL FOR AT24RF08CN-10SC RoHS:否 類別:RF/IF 和 RFID >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:用于 200/300 系列的歐盟開發(fā)套件 適用于相關(guān)產(chǎn)品:Zensys RF 模塊 所含物品:開發(fā)板，模塊，編程器，軟件，線纜，電源 其它名稱:703-1019Q3225667
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