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參數(shù)資料
| 型號： | AT24C128-W2.7-11 |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Two-wire Serial EEPROMs |
| 中文描述： | 16K X 8 I2C/2-WIRE SERIAL EEPROM, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 388K |
| 代理商： | AT24C128-W2.7-11 |
5
AT24C128/256
0670S–SEEPR–5/06
Table 4.
AC Characteristics – Industrial Temperatures
Applicable over recommended operating range from T
AI
=
–
40
°
C to +85
°
C, V
CC
= +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k
(2.5V, 5V), 10 k
(1.8V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
50 ns
Input and output timing reference voltages: 0.5 V
CC
3. The Write Cycle Time of 5 ms only applies to the AT24C128/256 devices bearing the process letter “B” on the package (the
mark is located in the lower right corner on the top side of the package).
4. The AT24C128/256 bearing the process letter “B” in the package (the mark is located in the lower right corner on the top
side of the package), guarantees 1 million write cycle endurance (1.8 – 3.6V).
Symbol
Parameter
1.8-volt
2.5-volt
5.0-volt
Units
Min
Max
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
100
400
1000
kHz
t
LOW
Clock Pulse Width Low
4.7
1.3
0.4
μs
t
HIGH
Clock Pulse Width High
4.0
0.6
0.4
μs
t
AA
Clock Low to Data Out Valid
0.1
4.5
0.05
0.9
0.05
0.55
μs
t
BUF
Time the bus must be free before a
new transmission can start
(1)
4.7
1.3
0.5
μs
t
HD.STA
Start Hold Time
4.0
0.6
0.25
μs
t
SU.STA
Start Set-up Time
4.7
0.6
0.25
μs
t
HD.DAT
Data In Hold Time
0
0
0
μs
t
SU.DAT
Data In Set-up Time
200
100
100
ns
t
R
Inputs Rise Time
(1)
1.0
0.3
0.3
μs
t
F
Inputs Fall Time
(1)
300
300
100
ns
t
SU.STO
Stop Set-up Time
4.7
0.6
0.25
μs
t
DH
Data Out Hold Time
100
50
50
ns
t
WR
Write Cycle Time
20
or
5
(3)
10
or
5
(3)
10
or
5
(3)
ms
Endurance
(1)
25°C, Page Mode
100k or 1,000,000
(4)
Write
Cycles
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