- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381398 > AT17LV512 (Atmel Corp.) 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) PDF資料下載
參數(shù)資料
| 型號： | AT17LV512 |
| 廠商： | Atmel Corp. |
| 英文描述： | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
| 中文描述： | 為512k FPGA配置存儲器（為512k現(xiàn)場可編程（FPGA）的配置的EEPROM存儲器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 212K |
| 代理商： | AT17LV512 |
AT17C/LV512/010
4
Pin Configurations
20
PLCC
Pin
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the “Programming Specification” application note for more details.
6
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
7
WP2
I
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the “Programming Specification” application note for more details.
8
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low-power standby mode. Note that this pin will not enable/disable the device in
the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).
10
GND
Ground pin. A 0.2 μF decoupling capacitor between VCC and GND is recommended.
14
CEO
O
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read
from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until
OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low; see the “Programming Specification” application note for
more details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (Recommend a 4.7 k
pull-up on this pin if used).
17
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
20
VCC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................ 2000V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT22LV10 | Low-Voltage UV Erasable Programmable Logic Device |
| AT22LV10-20JC | Circular Connector; No. of Contacts:12; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:32; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:32-6 RoHS Compliant: No |
| AT22LV10-20JI | 10-169232-05S |
| AT22LV10-20PC | Low-Voltage UV Erasable Programmable Logic Device |
| AT22LV10-20PI | Low-Voltage UV Erasable Programmable Logic Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV512-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10CC | 功能描述:FPGA-配置存儲器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV512-10CI | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV512-10CU | 功能描述:FPGA-配置存儲器 CONFIG SERIAL EEPROM 512K ALTERA PINOUT RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。