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參數(shù)資料
| 型號(hào)： | AT17LV512 |
| 廠商： | Atmel Corp. |
| 英文描述： | 512K FPGA Configuration EEPROM Memory(512K 現(xiàn)場(chǎng)可編程（FPGA）配置EEPROM存儲(chǔ)器) |
| 中文描述： | 為512k FPGA配置存儲(chǔ)器（為512k現(xiàn)場(chǎng)可編程（FPGA）的配置的EEPROM存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | AT17LV512 |
AT17C/LV512/010
3
Figure 1.
Condition 2 Connection
Notes:
1. Use of the READY pin is optional.
2. Reset polarity of EEPROM must be set active Low.
Condition 2
The FPGA CON output drives only the CE input of the
AT17 Series Configurator, while the RESET/OE input is
driven by the FPGA INIT pin (Figure 1). This connection
works under all normal circumstances, even when the user
aborts a configuration before CON has gone high. A Low
level on the RESET/OE
(1)
input – during FPGA reset –
clears the Configurator’s internal address pointer, so that
the reconfiguration starts at the beginning.
Note:
1. For this condition the reset polarity of the EEPROM
must be set active Low.
The AT17 Series Configurator does not require an inverter
for either condition since the RESET polarity is
programmable.
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line driver. The second Configurator rec-
ognizes the Low level on its CE input and enables its DATA
output.
After configuration is complete, the address counters of all
cascaded Configurators are reset if the RESET/OE on
each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE input can be tied to its inactive
(default Low) level.
AT17 Series Reset Polarity
The AT17 Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer
algorithms. For more details on programming the
EEPROMs reset polarity, please reference the “Program-
ming Specification for Atmel’s FPGA Configuration
EEPROMs” application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the “Programming Specification for Atmel’s
FPGA Configuration EEPROMs” application note for fur-
ther information. The AT17C parts are read/write at 5V
nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV512/010 Series Configurator enters a low-
power standby mode whenever CE is asserted High. In this
mode, the Configurator consumes less than 0.5 mA of cur-
rent at 5V. The output remains in a high impedance state
regardless of the state of the OE input.
M0
INIT
M1
CON
CCLK
D<0>
RESET
RESET
AT40K
AT17C512/010
AT17LV512/010
GND
VCC
RESET/OE
READY
SER_EN
CE
CLK
DATA
M2
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相關(guān)代理商/技術(shù)參數(shù) |
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| AT17LV512-10BJC | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10BJI | 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV512-10CC | 功能描述:FPGA-配置存儲(chǔ)器 2M bit FPGA RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV512-10CI | 功能描述:FPGA-配置存儲(chǔ)器 ASICS RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV512-10CU | 功能描述:FPGA-配置存儲(chǔ)器 CONFIG SERIAL EEPROM 512K ALTERA PINOUT RoHS:否 制造商:Altera Corporation 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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