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參數資料
| 型號： | ASM5I9352G-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-32 |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 475K |
| 代理商： | ASM5I9352G-32-ET |
July 2005
rev 0.2
DC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= -40°C to +85°C)
ASM5I9352
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
5 of
12
Notice: The information in this document is subject to change without notice.
Parameter
V
IL
Description
Condition
Min
1.7
1.8
Typ
5
Max
0.7
Unit
V
Input Voltage, Low
LVCMOS
V
IH
Input Voltage, High
Output Voltage, Low
1
Output Voltage, High
1
LVCMOS
V
DD
+ 0.3
V
V
OL
I
OL
= 15 mA
0.6
–10
V
V
OH
I
OH
= –15 mA
V
I
IL
Input Current, Low
Input Current, High
2
V
IL
= V
SS
μA
I
IH
V
IL
= V
DD
100
μA
I
DDA
PLL Supply Current
AV
DD
only
10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except AV
DD
3
5
mA
I
DD
Dynamic Supply Current
170
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Note:1.Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
Output Impedance
17 – 20
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
Description
Condition
Min
2.0
2.4
Typ
5
Max
0.8
Unit
V
Input Voltage, Low
LVCMOS
V
IH
Input Voltage, High
LVCMOS
V
DD
+ 0.3
V
I
OL
= 24 mA
0.55
V
OL
Output Voltage, Low
1
I
OL
= 12 mA
0.30
–10
V
V
OH
Output Voltage, High
1
I
OH
= –24 mA
V
I
IL
Input Current, Low
Input Current, High
2
V
IL
= V
SS
μA
I
IH
V
IL
= V
DD
100
μA
I
DDA
PLL Supply Current
AV
DD
only
10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except AV
DD
3
5
mA
I
DD
Dynamic Supply Current
240
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
14 – 17
Note:1.Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I9352G-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I961CG-32-ET | Low Voltage Zero Delay Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ASM5I9352G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I961C | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961CG-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
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