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參數(shù)資料
| 型號： | ASM5I9352G-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-32 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 475K |
| 代理商： | ASM5I9352G-32-ET |
July 2005
rev 0.2
ASM5I9352
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
3 of
12
Notice: The information in this document is subject to change without notice.
Pin Configuration
1
Pin
6
12, 14,
15, 18, 19
22, 23,
26, 27
30, 31
Name
REFCLK
I/O
I, PD
Type
LVCMOS
Description
Reference clock input
.
QA(0:4)
O
LVCMOS
Clock output bank A
.
QB(0:3)
O
LVCMOS
Clock output bank B
.
QC(0,1)
O
LVCMOS
Clock output bank C
.
Feedback clock input
. Connect to an output for normal operation.
This input should be at the same voltage rail as input reference
clock. See
Table 1
.
VCO divider select input
. See
Table 2
.
Master reset/output enable/disable input
. See
Table 2
.
PLL enable/disable input
. See Table 2.
Frequency select input, Bank (A:C)
. See
Table 2
.
2.5V or 3.3V power supply for bank A output clocks
2,3
.
2.5V or 3.3V power supply for bank B output clocks
.
2,3
2.5V or 3.3V power supply for bank C output clocks
.
2,3
2.5V or 3.3V power supply for PLL
.
2,3
2.5V or 3.3V power supply for core and inputs
.
2,3
Analog ground
.
8
FB_IN
I, PD
LVCMOS
1
VCO_SEL
I, PD
LVCMOS
5
MR/OE#
I, PD
LVCMOS
9
2, 3, 4
16, 20
21, 25
32
10
11
PLL_EN#
SEL(A:C)
V
DDQA
V
DDQB
V
DDQC
AV
DD
V
DD
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
LVCMOS
LVCMOS
V
DD
V
DD
V
DD
V
DD
V
DD
7
13, 17,
24, 28, 29
Note: 1. PD = Internal pull-down.
2.A 0.1μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
supply pins.
AV
SS
Supply
Ground
V
SS
Supply
Ground
Common ground
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9352G-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I961CG-32-ET | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9352G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I961C | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961CG-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
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