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參數(shù)資料
| 型號(hào)： | ASM5I9351G-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| 中文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-32 |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 522K |
| 代理商： | ASM5I9351G-32-ET |
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July 2005
rev 0.2
ASM5I9351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
Table 1: Frequency Table
Feedback Output
Divider
÷2
VCO
Input Frequency Range
(AVDD = 3.3V)
100 MHz to 200 MHz
Input Frequency Range
(AVDD = 2.5V)
100 MHz to 190MHz
Input Clock * 2
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95MHz
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5MHz
Table 2: Function Table
Control
REF_SEL
Default
0
0
1
PCLK
TCLK
PLL_EN
1
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
PLL enabled. The VCO output connects to
the output dividers
OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running
at its minimum frequency
÷ 4 (Bank A)
SELA
0
÷2 (Bank A)
SELB
0
÷4 (Bank B)
÷4 (Bank C
)
÷ 8 (Bank B)
SELC
0
÷ 8 (Bank C)
SELD
0
÷4 (Bank D)
÷ 8 (Bank D)
Absolute Maximum Ratings
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
Description
Condition
Min
–0.3
2.375
–0.3
–0.3
200
–65
–40
Max
5.5
3.465
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
÷2
150
+150
+85
+150
42
105
Unit
V
V
V
V
V
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Functional
Relative to V
SS
Relative to V
SS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Manufacturing test
LU
R
PS
T
S
T
A
T
J
JC
JA
ESD
H
FIT
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
2000
10
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9351G-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351 | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352G-32-ET | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
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